Debugging Approaches Sample Clauses

Debugging Approaches. Debugging stages follows the Bottom Up Modeling stages, and the integration phase. At every single module that have been build a test bench applies in order to certified that the its functionality is equivalent to the desired as it was described at Top Down analysis and the bottom up modeling. Several debugging tools are used, the most common of which are simulators as ISE simulator or ModelSim. More sophisticated tools are used for complex platforms as Vivado Simulator, Maxeler Simulator, Convey Software-Hardware Simulator. These tools usually provide to the designer a visualized representation of the system functionality. Modules debugging is a demanding procedure. It is very important to have the proper testing vectors for each module. Debugging and test vectors creation is better to be created from designers that have not be involved in modeling phase. This independent procedure helps to detect more problems as wrong or missing functionality. In order to have the proper test vectors, and for complex subsystems, the designer makes small applications to produce them. Simulations should be exhaustive for small modules and extensive for the most complex ones. Exhaustive simulation examines and proves the complete functionality of the system but it is very time demanding procedure. For this reason, for more complex systems an extensive simulation is usually performed. The system is examined at several different states for several thousand or millions clock cycles. A careful selection of states and test vectors should be done in order to test the complete module functionality. This procedure is repeated for every module that has been build. At integration phase it is repeated for every module added to the subsystem. The simulation phase starts with the functional model which specifies only the functionality of the model without any timing data, such as set up / hold time for example (these are timing constraints for proper clocking of sequential circuits). When the proper functionality has been checked for each module, a new simulation has to be done where a timing model for the target technology is included to test the module or the subsystem with timing parameters. The test vectors are the same, without any changes from stage to stage.
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