Common use of Control 1 Pin Clause in Contracts

Control 1 Pin. Programmable Control Pin 1 (PRG_CNTL1) is an input pin from the Host, operating with programmable logic. It is pulled up in the CFP module. It can be re-programmed over MDIO registers to another MDIO control register while the module is in any steady state except Reset. The CFP MSA specifies that the default function be Transmit & Receive circuitry reset (TRXIC_RSTn) with active-low logic. When TRXIC_RSTn is asserted (driven low) the digital transmit and receive circuitry is reset clearing all FIFOs and/or resetting all CDRs and/or DLLs. When de-asserted, the digital transmit and receive circuitry resumes normal operation.

Control 1 Pin. Programmable Control Pin 1 (PRG_CNTL1) is an input pin from the Host, operating with programmable logic. It is pulled up in the CFP module. It can be re-programmed over MDIO registers at run-time to another MDIO control register while the module is in any steady state except Resetregister. The CFP MSA specifies that the default function be Transmit & Receive circuitry reset (TRXIC_RSTn) with active-low logic. When TRXIC_RSTn is asserted (driven low) the digital transmit and receive circuitry is reset clearing all FIFOs and/or resetting all CDRs and/or DLLs. .. When de-asserted, the digital transmit and receive circuitry resumes shall resume normal operation.