Current Offer Low Power Tools at RT and Algorithm Sample Clauses

Current Offer Low Power Tools at RT and Algorithm. Level In the following, we briefly review the relevant tool developments concerning high-level power optimisation. Given the context of the project, tools addressing the logic level and below will not be considered. Software Level Software power estimation techniques operating at different levels of abstraction have been proposed. Most of the approaches analyse the code at assembly level relying on an RT- or behavioural-level model of the microprocessor. These methods suffer two major drawbacks: the need of an accurate description of the microprocessor core and extremely long simulation run times. Recently, these problems have been partially overcome by focusing on an abstract (functional) model of the processor. Prototype tools implementing this technique have been developed within the PEOPLE project. The toolset provides core characterisation and assembly-level software estimation capabilities. No reliable and widely applicable strategies working at source-level have been proposed in literature and no commercial or prototype tools are currently available. Concerning the power optimisation, many proposals focused on reducing the power consumed by memories, trying to minimize the need to access main memory through a careful management of data organisation, while exploiting the presence of caches. Other techniques operate at the instruction-level, and are based on a proper modelling of the microprocessor to provide power figures for each instruction. Power optimisation is then accomplished by selecting the best mix of instructions to execute the given application. A few techniques, still working on the code, for specific classes of applications can reduce power demand by decreasing the accuracy of computation within the limit of tolerability. Dynamic variable-voltage techniques have been also proposed, to reduce performance and power consumption, during the execution of weakly critical sub-tasks. Dynamic power management can be also employed at system level, by means of a suitable methodology forcing (sleep) low power states, when the system becomes inactive; both fixed and predictive strategies have been proposed. Hence, the task of managing the software-specific power-issues is not yet shifted toward EDA vendors. In particular, there is a lack of methodologies and tools working at source level both for estimation and optimisation of power consumption. Algorithm Level The research and development centre IMEC, Belgium, has developed a system level synthesis...