Wafer-to-Layer Processes Clause Samples

Wafer-to-Layer Processes. 3.1.2.1 The contractor shall use a molded integration approach that uses a CTE (Coefficient of Thermal Expansion) engineered material to form individual layers of large wafer-like structures up to 300 mm x 300 mm. These structures shall use KGD (Known Good Die) and built-in passive components. 3.1.2.2 The contractor shall investigate holding parts in a fixture and molding them into a layer using silica epoxies. Interconnects shall be formed using multilayer metal traces and through vias. The molded layer shall then be reduced to 50-200 microns in thickness. 3.1.2.3 The contractor shall investigate using a hydrophobic/hydrophilic surface preparation to establish conductive areas as a complement to the micro-springs. 3.1.2.4 The contractor shall investigate embedding discrete packaged capacitors into the molded layer. The contractor shall also fabricate multi-layer thin film capacitors on flex. 3.1.2.5 The contractor shall investigate the fabrication of multi-layer spiral inductors in the same flex technology as the capacitors in 3.1.2.4. 3.1.2.6 The contractor shall investigate whether SOI (Silicon On Insulator) and wafer level chips stacks can be accommodated as part of the stack layers. 3.1.2.7 The contractor shall design and fabricate low power reconfigurable interconnect layers.