MONETIZATION PROCEEDS AGREEMENT

Exhibit 99.17

Ex. H - MPA-MR

This Monetization Proceeds Agreement (the “Agreement”) dated as of February 19, 2021, is entered into by and between Intelligent Partners LLC, a Delaware limited liability company (as transferee of United Wireless Holdings, Inc.) (“IPLLC”), and M-Red Inc. (“MRED” or “Patent Owner”), a Texas corporation, and is effective as of the Restructure Date (as defined below). (IPLLC and the Patent Owner are collectively referred to herein as the “Parties” and each individually as a “Party.”)

RECITALS

MRED is party to a patent sale agreement dated March 15, 2019 by and between MRED, Intellectual Ventures 113 LLC and Intellectual Ventures Assets 108 LLC (the “IV 113/108 Agreement”) pursuant to which MRED acquired all right, title and interest to the United States patents and related assets identified on Exhibit A attached hereto; and

MRED is a wholly owned subsidiary of Quest Patent Research Corporation, a Delaware corporation (the “Company”); and

Company, Patent Owner and IPLLC are parties to that certain Restructure Agreement dated as even date hereof (“Restructure Agreement”): and

It is a condition precedent to IPLLC’s entering into the Restructure Agreement that MRED execute and deliver to IPLLC an agreement in substantially the form hereof;

NOW, THEREFORE, in consideration for the mutual agreements contained herein, and other good and valuable consideration, the receipt and sufficiency of which is hereby acknowledged, the Parties, intending to be legally bound, agree as follows:

1. CONSTRUCTION

1.1. For purposes of this Agreement, defined terms shall have the meanings set forth in Section 2 below. Capitalized terms used herein and not otherwise defined herein shall have the respective meanings provided therefor in the Restructure Agreement.

1.2. Headings are for information only and do not form part of the operative provisions of this Agreement.

1.3. References to this Agreement include references to the Recitals.

1.4. In this Agreement, unless a clear contrary intention appears: (a) words denoting the singular include the plural and vice versa; (b) words denoting any gender include all genders; (c) all references to ”$” or dollars shall mean U.S. Dollars; (d) the word “or” shall include both the adjunctive and the disjunctive meaning thereof; and (e) the words “include,” “includes,” and “including” shall be deemed to be followed by the phrase “without limitation.”

1.5. The terms of this Agreement have been negotiated between the Parties in an arm’s length transaction, and shall not be construed for or against either Party by reason of the drafting or preparation hereof.

2. DEFINITIONS The following terms shall have the meanings given below:

2.1 “Acceleration Event” means: (a) the sale, transfer, assignment or other conveyance of more than fifty percent (50%) of the Patents to an entity other than an Affiliate of Patent Owner; (b) the sale of all or substantially all of the outstanding capital stock or operating assets (other than cash) of Patent Owner; or (c) a material breach (including non-payment) by Patent Owner under this Agreement that is not cured within thirty (30) days after written notice thereof from IPLLC to Patent Owner.

2.2 “Affiliate” means, with respect to any Person, any Entity in whatever country organized, that Controls, is Controlled by or is under common Control with such Person.

2.3 “Confidential Information” means all documents and information (whether written or oral), including all communications, contracts, and agreements, exchanged by the Parties related to the Parties' relationship, or the Patents. The term Confidential Information does not include information that: (i) becomes generally available to the public other than as a result of a breach by a Party of this Agreement, (ii) is already in the receiving Party's possession, provided that such information is not known by the receiving Party to be subject to a contractual or legal obligation of confidentiality to the disclosing Party, or (iii) becomes available to the receiving Party on a non-confidential basis from a source other than the disclosing Party, provided that such source is not known by the receiving Party to be bound by a contractual or legal obligation of confidentiality to the disclosing Party.

2.4 “Control” (or such other conjugations) for the purpose of this Agreement means the direct or indirect ownership of more than fifty percent (50%) of the shares or similar equity interests or voting power of the outstanding voting securities of such Entity that represent the power to direct the management and policies of such Entity.

2.5 “Costs” means, excluding Fees, the actual and reasonable out-of-pocket costs incurred by or for Patent Owner and paid to a non-Affiliate third party for:

(a) Any payment of the Purchase Price as defined in and pursuant to the IV 113/108 Agreement after the date hereof, provided Patent Owner agrees not to pay any portion of the Purchase Price in excess of the Further Payment obligation toward a Minimum Payment obligation which is due more than 12 months from the date of receipt of the applicable Net Proceeds; and,

(b) any required patent maintenance fees, patent prosecution costs, whether for administrative proceedings, re-examinations, re-issues, continuations, and the like; and

(c) enforcement costs (including but not limited to, filing fees, translation costs, testifying and non-testifying experts, visual aids, court costs, deposition fees, document reproduction costs, discovery costs, on-line research costs),

all in connection with the effort to license, sell, or otherwise monetize the Patents. For the avoidance of doubt, (i) Patent Owner and its Affiliates’ or law firm’s operating, administrative, personnel and similar costs and (ii) financing premiums, interest, and any amounts over and above the actual out-of-pocket amounts advanced are not included in the definition of “Costs.”

2.6 “Disputes” has the meaning set forth in Section 6.3.

2.7 “Entity” means any corporation, partnership, limited liability company, association, joint stock company, trust, joint venture, unincorporated organization, governmental entity (or any department, agency, or political subdivision thereof) or any other legal entity.

2.8 “Fees” means the reasonable amount of fees (excluding Costs) payable to third party attorneys, law firms, Litigation Funders, consultants and/or licensing professionals as compensation, contingent or otherwise, for achieving any Gross Monetization Proceeds. Such fee arrangements shall be reasonable and in accordance with market rates for such financing and/or legal services, as the case may be.

2.9 “Gross Monetization Proceeds” means Patent Owner and its Affiliates’ gross revenue and/or other consideration from the sale, licensing and/or other monetization activities related to the Patents after the Restructure Date. Patent Owner and its Affiliates’ gross revenue shall be as determined according to United States generally accepted accounting principles (U.S. GAAP) or an international equivalent.

2.10 “Litigation Financing” means capital provided to Patent Owner by a Litigation Funder for the purpose of achieving any Gross Monetization Proceeds.

2.11 “Litigation Funder” means any Person providing Litigation Financing to Patent Owner.

2.12 “Monetization” means the sale, licensure, enforcement or otherwise monetize the Patents.

2.13 “Net Proceeds” means Gross Monetization Proceeds minus the sum of Costs and Fees.

2.14 “Net Proceeds Percentage” means sixty percent (60%) of any Net Proceeds derived from the Patents, provided that in the event any single transaction yields in excess of $3,000,000 in Net Proceeds due to the Patent Owner, the Net Proceeds Percentage shall increase to eighty percent (80%) on the portion of such single transaction’s Net Proceeds in excess of $3,000,000.

2.15 “Patents” means the patents and related assets identified on Exhibit A and Exhibit B attached hereto and all patents and patent applications related thereto, and all patents and patent applications claiming benefit, in whole or in part, of any of their filing dates including, but not limited to, extensions, divisionals, continuations, continuations-in-part, reissues, reexaminations, substitutions and foreign counterparts of any of the foregoing, the inventions disclosed or claimed therein, including the right to make, use, practice and/or sell (or license or otherwise transfer or dispose of) the inventions disclosed or claimed therein, and the right (but not the obligation) to make and prosecute applications for such patents.

2.16 “Patent Owner’s Attorney” means any legal counsel engaged to represent any Patent Owner in connection with Monetization.

2.17 “Patent Proceeds Security Agreement” has the meaning given to that term in the Restructure Agreement.

2.18 “Person” means any individual, firm, company, corporation, partnership, limited liability company, government, state, or agency, or subdivision of a state (or governmental entity), or any association, trust, joint venture, or consortium (whether or not having separate legal personality).

2.19 “Representative” means the employees, officers, directors, partners, members, shareholders (other than shareholders of QPRC solely in their capacity as such), co-investors, potential co-investors, agents, advisors, consultants, accountants, attorneys, trustees, or authorized representatives of a Party.

2.20 “Restructure Date” shall have the meaning ascribed thereto in the Restructure Agreement.

2.21 “Rights” means all rights, titles, claims, options, powers, privileges, and interests.

2.22 “Security” means a mortgage, charge, pledge, lien, or other security interest securing any obligation of any Person or any other agreement or arrangement having a similar effect.

2.23 “Senior Liens” means any Security in the Collateral, as defined in the Patent Proceeds Security Agreement, granted to: (a) Intellectual Ventures Assets 113, LLC pursuant to the Security Interest Addendum dated Xxxxx 00, 0000 (x) Intellectual Ventures Assets 108, LLC pursuant to the Security Interest Addendum dated March 15, 2019 (c) QPRC Finance, LLC pursuant to the Purchase Agreement and Investment Documents (as defined in the Restructure Agreement), and; (d) any Security in the Collateral that Patent Owner may in the future grant to a Litigation Funder or Patent Owner’s Attorney in conjunction with funding or representation relating to Monetization efforts, limited to the amount of the Patent Owner’s obligations under the related litigation financing or retainer agreements.

2.24 “Taxes” means any non-U.S., U.S. federal, state, local, municipal, or other governmental taxes, duties, levies, fees, excises, or tariffs, arising as a result of or in connection with any amounts of property received or paid under this Agreement, including: (i) any state or local sales or use taxes; (ii) any import, value-added, consumption, or similar tax; (iii) any business transfer tax; (iv) any taxes imposed or based on or with respect to or measured by any net or gross income or receipts of any of the Parties; (v) any withholding or franchise taxes, taxes on doing business, gross receipts taxes or capital stock or property taxes; or (vi) any other tax now or hereafter imposed by any governmental or taxing authority on any aspect of this Agreement, the Gross Monetization Proceeds, or the Net Proceeds, and “pre-Tax” shall mean before deduction of any of the foregoing except for unavoidable foreign taxes for which the Patent Owner is legally liable, provided that the Patent Owner uses commercially reasonable efforts to minimize any such taxes.

2.25 “Total Monetization Proceeds Obligation” has the meaning ascribed thereto in the Restructure Agreement

3. PROCEEDS.

3.1 Assignment of the Net Proceeds Percentage. Patent Owner hereby irrevocably assigns to IPLLC the Net Proceeds Percentage of the Net Proceeds in perpetuity.

3.2 Payment of the Net Proceeds Percentage; Reduction of Total Monetization Proceeds Obligation. IPLLC shall be entitled to receive an amount equal to the Net Proceeds Percentage of all Net Proceeds, payable out of all Net Proceeds received or entitled to be received by or transferred, paid or inuring to Patent Owner, from whatever source (“IPLLC Proceeds Payments”), and all IPLLC Proceeds Payments made pursuant to this Agreement shall be applied against and reduce the then outstanding Total Monetization Proceeds Obligation on a dollar for dollar basis, if any, as of the date of any such IPLLC Proceeds Payment.

3.3 Disbursement of Net Proceeds. Patent Owner shall calculate and provide a written report to IPLLC (as set forth in Section 3.5 below) of the amount of Net Proceeds due to Patent Owner and IPLLC at the same time any disbursement notice documentation is provided to attorneys, law firms, QFL, litigation funding sources, patent sellers/prior owners, licensing professionals/consultants or other Persons entitled to payment upon receipt of Gross Monetization Proceeds and then shall pay or cause IPLLC to be paid the IPLLC Proceeds Payment pursuant to this Section 3.3 at the same time as the Patent Owner receives any Net Proceeds.

3.4 Acceleration; Guarantee. All outstanding IPLLC Proceeds Payments under this Agreement shall become due and payable upon the occurrence of an Acceleration Event, in addition to any other remedies IPLLC may have at law or in equity. In the event any Gross Monetization Proceeds are received by an Affiliate or Affiliates of Patent Owner, Patent Owner and each such Affiliate will be jointly and severally responsible for the payment and reporting to IPLLC of the IPLLC Proceeds Payments owed pursuant to Sections 3.2, 3.3, 3.4 and 3.5 of this Agreement. For the avoidance of doubt and subject to the provisions of Section 5.1(c) below, no Affiliate of Patent Owner makes any guarantee of Patent Owner’s payment obligations under this Agreement.

3.5 Reporting. All reports shall be in the English Language and in sufficient detail such that IPLLC can reasonably verify the IPLLC Proceeds Payments due to IPLLC. Each report shall be certified in advance by an officer of Patent Owner or by a designee of such officer to be correct to the best knowledge and information of Patent Owner. Reports shall be sent to IPLLC by electronic mail to xxxxxx.xxxxxx@xxxxxxxxxxxxxxxxxxxxxx.xxx and xxxx.xxxxxx@xxxxxxxxxxxxxxxxxxxxxx.xxx , or as IPLLC otherwise directs from time to time in a written notice to Patent Owner.

3.6 Access; Audit. Patent Owner and each of its Affiliates that receive any Gross Monetization Proceeds shall keep and maintain true and complete books and records pertaining to monetization of the Patents in sufficient detail to enable the amounts payable to IPLLC to be accurately determined. In addition, without limiting any access or audit rights of IPLLC provided for in the Restructure Agreement, no more than once each year and upon at least five (5) business days prior written notice to Patent Owner, Patent Owner shall make such books and records related to this Agreement available at reasonable times during regular business hours for inspection and copying by IPLLC, or their designated representatives, and supply IPLLC with the details and supporting data necessary to verify the reports and payments required by this Agreement. Patent Owner and such Affiliates shall maintain such books and records related to this Agreement for at least five (5) years after the end of the calendar year to which they pertain. In the event any such inspection shows an underpayment of IPLLC Proceeds Payments by Patent Owner or one of its Affiliates for any calendar-quarter period, Patent Owner shall promptly pay to IPLLC any such amounts plus a Late Payment Charge, as defined in the Restructure Agreement. Furthermore, if such underpayment is more than the greater of (A) 5% of the total IPLLC Proceeds Payments due for the period audited or (B) $10,000, or if the audit shows that any under-reporting was willful, Patent Owner or such Affiliates shall reimburse IPLLC for the cost of the inspection within thirty (30) days after any such finding of underpayment.

3.7 Security. Patent Owner’s obligation to pay the IPLLC Proceeds Payments shall be secured under the terms of the Patent Proceeds Security Agreement, and if requested by the Patent Owner, IPLLC agrees to execute a subordination agreement with respect to the security interest created thereby with any Senior Lien holder, in form reasonably acceptable to IPLLC and the Senior Lien holder. For the avoidance of doubt, neither this Agreement nor the Patent Proceeds Security Agreement is a guarantee by any Affiliate of Patent Owner of Patent Owner’s payment obligations under this Agreement.

4. REPRESENTATIONS AND WARRANTIES

4.1. Patent Owners’ Representations and Warranties. Patent Owner makes the representations, warranties, and Covenants set out in this Section as of the date of this Agreement and for the duration of this Agreement, except as may be disclosed in writing to IPLLC for events that arise subsequent to the date of this Agreement:

(a) Patent Owner is a corporation duly formed, validly existing, and in good standing under the laws of the jurisdiction of its formation;

(b) Patent Owner has all requisite power and authority to enter into, execute, and deliver this Agreement and to perform fully its obligations hereunder;

(d) To Patent Owner’s knowledge, no third party of has the right to grant any licenses in and to any of the Patents; and

(e) To Patent Owner’s knowledge, there are no inventorship challenges, opposition, reexamination, or nullity proceedings or interferences declared, commenced or provoked, or to the knowledge the Patent Owner, threatened, with respect to any Patents. The Patent Owner has no knowledge of any information that would preclude Patent Owner from having clear title to the Patents or affecting their patentability, validity, or enforceability.

4.2. IPLLC Representations and Warranties. IPLLC makes the representations, warranties, and Covenants set out in this Section as of the date of this Agreement and for the duration of this Agreement, except as may be disclosed in writing to Patent Owner for events that arise subsequent to the date of this Agreement:

(a) IPLLC is a corporation duly formed, validly existing, and in good standing under the laws of the jurisdiction of its formation;

(b) IPLLC has all requisite power and authority to enter into, execute, and deliver this Agreement and to perform fully its obligations hereunder;

5. ADDITIONAL COVENANTS AND TAXES

5.1. Covenants. For so long as the Patent Owner holds the Patents, any amount is outstanding, or obligation of Patent Owner is remaining under this Agreement, Patent Owner shall (unless it has obtained prior written consent from IPLLC to the contrary), at its sole cost and expense:

(a) not, except for the Senior Liens, grant or create or allow any other Person other than IPLLC to hold any superior Security over the Patents or the Gross Monetization Proceeds, or any rights thereto;

(b) not, except as permitted under the IV Agreements, the Purchase Agreement, the Investment Documents or any Litigation Funding agreement, transfer, sell, assign, or otherwise dispose of any of its Rights in or under any of the contracts or agreements relating to the Gross Monetization Proceeds; and

(c) not transfer, sell, assign, or otherwise dispose of any of the Patents, except as permitted under the IV Agreements and provided any such future assignee or transferee of the Patents agree in writing to be bound to all payment, reporting and audit obligations of Patent Owner as set forth in this Agreement.

5.2. Taxes. All Taxes shall be the financial responsibility of the Party obligated to pay such Taxes as determined by applicable law and neither Party is or shall be liable at any time for any of the other Party’s Taxes incurred in connection with or related to amounts paid under this Agreement. Except for unavoidable foreign taxes for which the Patent Owner is legally liable, provided that the Patent Owner uses commercially reasonable efforts to minimize any such taxes, no Tax shall be withheld on any Gross Monetization Proceeds or other amounts payable to IPLLC hereunder unless required by law. If any applicable law requires the deduction or withholding of any tax from any such payment to IPLLC, then the Patent Owner shall be entitled to make such deduction or withholding and shall timely pay the full amount deducted or withheld to the relevant taxing authority in accordance with applicable law and the sum payable to IPLLC shall be increased as necessary so that, after such deduction or withholding has been made, IPLLC receives an amount equal to the sum it would have received had no such deduction or withholding been made. Each Party shall indemnify, defend and hold the other Party harmless from and against any Taxes owed by or assessed against the other Party that are the obligations of such Party and from any claims, causes of action, costs, expenses, reasonable attorneys’ fees, penalties, assessments and any other liabilities of any nature whatsoever related to such Taxes.

6. GOVERNING LAW; WAIVER OF SPECIFIC DEFENSES; DISPUTES

6.1. Governing Law. This Agreement and the rights and obligations of the parties hereunder shall be governed by the laws of the State of New York, without giving effect to any choice of law or conflict of law provision or rule, and shall be construed and enforced in accordance with the law.

6.2. Specific Waivers. To the greatest extent permissible by law, Patent Owner irrevocably waives and forever and unconditionally releases, discharges and quitclaims any claims, counterclaims, defenses, causes of action, remedies, or rights it or its successors in interest has or may in the future have arising from any doctrine, rule, or principle of law or equity that this Agreement, or the relationships or transactions contemplated by this Agreement (i) are against the public policy of any jurisdiction with which Patent Owner has a connection, or (ii) are unconscionable, or (iii) constitute champerty, maintenance, barratry, or any impermissible transfers, assignments or splitting of property, fees or causes of action.

6.3. Arbitrable Claims. All actions, disputes, claims and controversies under common law, statutory law, rules of professional ethics, or in equity of any type or nature whatsoever, whether arising before or after the date of this Agreement, and directly relating to: (a) this Agreement or any amendments and addenda hereto, or the breach, invalidity or termination hereof; (b) any previous or subsequent agreement between IPLLC and Patent Owner related to the subject matter hereof to the extent set forth in Section 8.2; (c) any act or omission committed by IPLLC or its Representatives with respect to this Agreement, or by any member, employee, agent, or lawyer of IPLLC with respect to this Agreement, whether or not arising within the scope and course of employment or other contractual representation of IPLLC (provided that such act arises under a relationship, transaction or dealing between IPLLC and Patent Owner); or (d) any act or omission committed by Patent Owner with respect to this Agreement, or by any employee, agent, partner or lawyer of Patent Owner with respect to this Agreement whether or not arising within the scope and course of employment or other contractual representation of Patent Owner (provided that such act arises under a relationship, transaction or dealing between IPLLC and Patent Owner) (collectively, the “Disputes”), will be subject to and resolved by binding arbitration under this Section 6.3 and Section 6.4 below, provided however, that nothing in this Section 6 shall limit the rights, if any, of IPLLC to commence or maintain judicial proceedings pursuant to the Restructure Agreement and other Restructure Documents. The Parties agree that the arbitrators have exclusive jurisdiction, to the exclusion of any court (except as specifically provided with regard to prejudgment, provisional, or enforcement proceedings in Section 6.5), to decide all Disputes.

6.4. Administrative Body; Situs. Any Dispute arising out of or relating to this Agreement, including the breach, termination, enforcement, interpretation or validity thereof, or the determination of the scope or applicability of this Agreement to arbitrate, shall be determined by arbitration in New York, New York, before a single arbitrator. The arbitration shall be administered using the arbitration rules of the American Arbitration Association (“AAA”) current at the time the Dispute is brought, which rules are deemed to be incorporated herein by reference. Each Party shall, upon written request, promptly provide the other Party with copies of all information on which the producing party may rely in support of or in opposition to any claim or defense and a report of any expert whom the producing Party may call as a witness in the arbitration hearing.

6.5. Prejudgment and Provisional Remedies. Either Party may commence judicial proceedings under this Agreement only for the purpose(s) of: (i) enforcement of the arbitration provisions; (ii) obtaining appointment of arbitrator(s); (iii) preserving the status quo of the Parties pending arbitration as contemplated herein; (iv) preventing the disbursement by any Person of disputed funds; (v) preserving and protecting the rights of either Party pending the outcome of the arbitration, or (vi) seeking injunctive relief for breach of the confidentiality provisions contained in Section 7. Any such action or remedy will not waive a Party’s right to compel arbitration of any Dispute, and any Party may also file court proceedings to have judgment entered on the arbitration award. In any action for prejudgment or provisional relief, any court in which such relief is sought shall determine the availability of such relief without regard to any defenses that may be asserted by the other Party, and any such defenses shall be referred to the exclusive jurisdiction of the arbitrators under Section 6.3. The Parties further agree that a court shall not defer or delay granting prejudgment or provisional relief while any such arbitration takes place. EACH PARTY HERETO HEREBY IRREVOCABLY WAIVES ANY RIGHT IT MAY HAVE, AND AGREES NOT TO REQUEST, A JURY TRIAL FOR THE ADJUDICATION OF ANY DISPUTE HEREUNDER OR IN CONNECTION WITH OR ARISING OUT OF THIS AGREEMENT OR ANY TRANSACTION CONTEMPLATED HEREBY.

6.6. Attorneys’ Fees. If Patent Owner or IPLLC brings any other action for judicial relief with respect to any Dispute (other than those precisely described in Section 6.5), the Party bringing such action will be liable for and immediately pay all of the other Party’s costs and expenses (including attorneys’ fees) incurred to stay or dismiss such action and remove or refer such Dispute to arbitration. If Patent Owner or IPLLC brings or appeals an action to vacate or modify an arbitration award and such Party does not prevail, such Party will pay all costs and expenses, including attorneys’ fees, incurred by the other Party in defending such action.

6.7. Enforcement. Any award rendered under this Section shall not be subject to appeal and shall be enforceable in any and all jurisdictions, including the State of Texas and the State of New York.

6.8. Confidentiality of Awards. All arbitration proceedings, including testimony or evidence at hearings, will be kept confidential, although any award or order rendered by the arbitrator(s) pursuant to the terms of this Agreement may be confirmed as a judgment or order in any state or federal or other national court of competent jurisdiction where proceedings are necessary or appropriate to enforce any award or order. This Agreement concerns transactions involving commerce among several state and foreign countries.

7. CONFIDENTIALITY

7.1. Confidential Information. The Parties shall limit the distribution and disclosure of Confidential Information to their Representatives who have a “need to know” to such information. The Party disclosing the Confidential Information to its Representatives shall ensure that such Representatives adhere to, and comply with, all terms and obligations of confidentiality, use and protection of the Confidential Information as accepted by the Parties under this Agreement.

7.2. Limitations on Disclosure of Confidential Information. The Parties and their Representatives shall not disclose Confidential Information, or the fact that the Parties entered into this Agreement, unless: (i) the Parties agree in writing that such disclosure is acceptable, (ii) such disclosure is required in connection with the enforcement or protection of a Party’s rights with respect to this Agreement, or (iii) such disclosure is required by law or regulation, governmental or regulatory authority, court order or judicial process; provided, that each Party agrees to give the other Party (to the extent not prohibited by applicable law, regulation, governmental or regulatory authority, court order or judicial process) written notice of any required disclosure and cooperate in obtaining a protective order or similar protection to preserve the confidential nature of the Confidential Information.

7.3. Public Disclosure. Neither IPLLC nor the Patent Owner shall issue any press release or make any public statement with respect to the existence of this Agreement or the transaction contemplated hereby, except as may be required by applicable law, regulation, governmental, or regulatory authority, judicial process, or court order. IPLLC and Patent Owner shall keep this Agreement confidential and not disclose it, or any part of it, or any drafts of it, to third parties, except as may be required by applicable law, regulation, governmental or regulatory authority, judicial process, or court order.

7.4. Information; Disclosure. Subject to Section 8.1, during any active Monetization, Patent Owner shall keep IPLLC reasonably informed of the progress of such monetization efforts, including prompt notice of events giving rise to Gross Monetization Proceeds, and prompt provision to IPLLC of any notice of settlement or proposed distribution notice provided to any other Person. These information and disclosure obligations shall terminate upon full payment of the Total Monetization Proceeds Obligation. For the avoidance of doubt, nothing in this Agreement shall be construed to require public disclosure of material non-public information and the Patent Owner shall not be required to provide notice or copies of documents filed on XXXXX, with the PTO, available on PACER or otherwise available to the public.

8. MISCELLANEOUS

8.1. Privileged Information. IPLLC will not request from the Patent Owner, and Patent Owner is not required to provide to IPLLC, documents and information protected by the attorney-client privilege. Patent Owner understands and acknowledges that in the event its Representatives provide privileged information to IPLLC, such disclosure may be deemed waiver of the applicable privilege. In the event that the Patent Owner inadvertently provides privileged information to IPLLC, IPLLC will return such information to Patent Owner without reviewing the information.

8.2. Entire Agreement and Amendments. This Agreement and the Restructure Documents constitute the entire agreement between the Parties with respect to the matters covered herein and supersede all prior agreements, promises, representations, warranties, statements, and understandings with respect to the subject matter hereof as between the Patent Owner and IPLLC. This Agreement may not be amended, altered, or modified except by an amendment or supplement to this Agreement executed by all Parties hereto and consented to by QFL.

8.3. Partial Invalidity; Severability. If, at any time, any provision of this Agreement is or becomes illegal, invalid or unenforceable in any respect under any law of any jurisdiction, neither the legality, validity or enforceability of the remaining provisions nor the legality, validity or enforceability of such provisions under the law of any other jurisdiction shall in any way be affected or impaired.

8.4. Remedies and Waivers. No failure to exercise, nor any delay in exercising, on the part of IPLLC or the Patent Owner, of any right or remedy under this Agreement shall operate as a waiver, nor shall any single or partial exercise of any right or remedy prevent any further or other exercise or the exercise of any other right or remedy. The rights and remedies provided in this Agreement are cumulative and not exclusive of any rights or remedies provided by law. No provision of this Agreement may be waived except in writing signed by the party granting such waiver.

8.5. Assignment. This Agreement shall inure to the benefit of, and be binding upon the respective successors and assigns of the Parties. The Patent Owner shall not assign or delegate its rights or obligations under this Agreement without the prior written consent of IPLLC, which shall not be unreasonably withheld.

8.6. Notices. All notices, reports and other communications required or permitted under this Agreement shall be as provided in the Restructure Agreement.

8.7. Term, Termination, Survival After Termination. This Agreement shall terminate at the earlier of (i) six years after the last to expire of the Patents owned by Patent Owner or (ii) mutual written agreement of the Parties (the period from the Restructure Date to the date of such termination, the “Term”). The provisions of Sections 1, 2 (with respect to applicable defined terms), 3.2 through 3.4, 6, 7, and 8 shall survive the termination of this Agreement.

8.8. Costs and Expenses. The Parties shall be solely responsible for and bear the costs and expenses, including attorneys’ fees, expenses of accountants, brokers, financial advisors, and other representatives and advisors, each incurs at any time in connection with pursuing, or consummating the transaction contemplated by, this Agreement.

8.9. No Presumption against Drafter. This Agreement has been negotiated by the Parties and their respective counsel and will be fairly interpreted in accordance with its terms and without any strict construction in favor of or against a Party.

8.10. Counterparts. This Agreement may be executed in counterparts which, when read together, shall constitute a single instrument, and this has the same effect as if the signatures on the counterparts were on a single copy hereof. A composite copy of this Agreement may be compiled comprising a single copy of the text of this Agreement and one or more copies of the signature pages containing collectively the signatures of all Parties. A facsimile or an electronic mail signature shall be considered due execution and shall be binding upon the signatories hereto with the same force and effect as if the signature were an original, not a facsimile signature.

8.11. Third-Party Beneficiaries. This Agreement is for the sole benefit of the parties hereto, their respective successors and permitted assigns and QFL and nothing herein, express or implied, is intended to or shall confer upon any other Person or entity any legal or equitable right, benefit or remedy of any nature whatsoever under or by reason of this Agreement. QFL is an intended third-party beneficiary of this Agreement.

[Signature pages follow]

IN WITNESS WHEREOF, the Parties execute this Agreement effective as of the Restructure Date.

	M-RED INC.

	By:	/s/ Xxx X. Xxxxxxx
	Name:	Xxx X. Xxxxxxx
	Title:	Chief Executive Officer

	INTELLIGENT PARTNERS LLC

	By:	/s/ Xxxxxx X. Xxxxxx
	Name:	Xxxxxx X. Xxxxxx
	Title:	Manager

[Signature Page to MPA-MR]

PATENTS

EXHIBIT A

Patent/ Application Number	Country	Issue Date/ Filing Date	Title of Patent and Inventors
6853259 (09/930822)	US	2/8/2005 (8/15/2001)	RING OSCILLATOR DYNAMIC ADJUSTMENTS FOR AUTO CALIBRATION Xxxxxxx X. Xxxxxxx; Xxxxxx X Xxxxxx
7068557 (11/042689)	US	6/27/2006 (1/25/2005)	RING OSCILLATOR DYNAMIC ADJUSTMENTS FOR AUTO CALIBRATION Xxxxxxx X. Xxxxxxx; Xxxxxx X Xxxxxx
7209401 (11/415771)	US	4/24/2007 (5/2/2006)	Ring oscillator dynamic adjustments for auto calibration Xxxxxx X. Xxxxxx; Xxxxxxx X. Xxxxxxx
6221682 (09/321565)	US	4/24/2001 (5/28/1999)	METHOD AND APPARATUS FOR EVALUATING A KNOWN GOOD DIE USING BOTH WIRE BOND AND FLIP-CHIP INTERCONNECTS Xxxxx X Xxxxxxxx; Xxxxxx Xxxx
RE43607 (11/809901)	US	8/28/2012 (5/31/2007)	Method and apparatus for evaluating a known good die using both wire bond and flip-chip interconnects Xxxxxxxx, Xxxxx X.; Xxxx, Xxxxxx
6177843 (09/320057)	US	1/23/2001 (5/26/1999)	OSCILLATOR CIRCUIT CONTROLLED BY PROGRAMMABLE LOGIC Xxxxxx X. Xxxxxxxx; Xxxxxxx Xxxx; Xxxx X. Xxxxx
6628171 (09/767989)	US	9/30/2003 (1/23/2001)	METHOD, ARCHITECTURE AND CIRCUIT FOR CONTROLLING AND/OR OPERATING AN OSCILLATOR Xxxxxx X. Xxxxxxxx; Xxxx X. Xxxxx; Xxxxxxx Xxxx
6831690 (09/456206)	US	12/14/2004 (12/7/1999)	ELECTRICAL SENSING APPARATUS AND METHOD UTILIZING AN ARRAY OF TRANSDUCER ELEMENTS Xxxxx-Xxxxxx Xxxx; Xxxx Xxx; Xxxxxx Xxxxxxxxxxx
JP5051939 (JP2000-369881)	JP	8/3/2012 (12/5/2000)	ELECTRIC SENSOR DEVICE, METHOD FOR GENERATING ELECTRIC SIGNAL FROM ARRAY OF CONVERTER ELEMENT XXXXXXXXXXX XXXXXX; XXX XXXX; XXXXX-XXXXXX XXXX
7511754 (10/973368)	US	3/31/2009 (10/26/2004)	Electrical sensing apparatus and method utilizing an array of transducer elements Xxxx Xxxxx-Xxxxxx; Xxxx Xxx; Xxxxxx Xxxxxxxxxxx
6498399 (09/391721)	US	12/24/2002 (9/8/1999)	LOW DIELECTRIC-CONSTANT DIELECTRIC FOR ETCHSTOP IN DUAL DAMASCENE BACKEND OF INTEGRATED CIRCUITS Xxxxx Xxxxx; Xxxxx Xxx
6744311 (10/128049)	US	6/1/2004 (4/23/2002)	SWITCHING AMPLIFIER WITH VOLTAGE-MULTIPLYING XXXXXX XXXXX Xxxxx Xxxx
0000000 (10/072461)	US	11/11/2003 (2/7/2002)	Programmable Logic Device Including Bi-Directional Shift Register Ankur Bal
6721310 (10/000272)	US	4/13/2004 (11/2/2001)	MULTIPORT NON-BLOCKING HIGH CAPACITY ATM AND PACKET SWITCH Xxxxx Xxx; Xxxxx Xxxx; Jiu An; Xxxxxx X. Xxxxxx
FR2790328 (FR9902658)	FR	4/20/2001 (2/26/1999)	Inductive Component, Integrated Transformer, In Particular For A Radio Frequency Circuit, And Associated Integrated Circuit With Such Inductive Component Or Integrated Transformer LAURENT BARTERS; MHANI AHMED; XXXXXXXX XXXXXXXX; XXXXX XXXX XXXXXX

Patent/ Application Number	Country	Issue Date/ Filing Date	Title of Patent and Inventors
6456183 (09/511748)	US	9/24/2002 (2/24/2000)	Inductor For Integrated Circuit Xxxx-Xxxxxx Xxxxx; Ahmed Mhani; Laurent Basteres; Xxxxxxxx Xxxxxxxx
6838970 (10/206284)	US	1/4/2005 (7/26/2002)	Inductor For Integrated Circuit Laurent Basteres; Ahmed Mhani; Xxxxxxxx Xxxxxxxx; Xxxx-Xxxxxx Xxxxx
FR2791470 (XX0000000)	FR	6/1/2001 (3/23/1999)	Monolithic Integrated Circuit Comprising An Inductor And A Method Of Fabricating The Same Xxxx-Xxxxxx Xxxxx; Ahmed Mhani; Laurent Basteres; Xxxxxxxx Xxxxxxxx
6459135 (09/525840)	US	10/1/2002 (3/15/2000)	Monolithic Integrated Circuit Incorporating An Inductive Component And Process For Fabricating Such An Integrated Circuit Xxxx-Xxxxxx Xxxxx; Ahmed Mhani; Laurent Basteres; Xxxxxxxx Xxxxxxxx
6388322 (09/764192)	US	5/14/2002 (1/17/2001)	Article comprising a mechanically compliant bump Xxxxx X. Xxxxxxx; Xxxxxxx X. Jan
6458411 (09/971764)	US	10/1/2002 (10/5/2001)	Method of making a mechanically compliant bump Xxxxx X. Xxxxxxx; Xxxxxxx X. Jan
6506648 (09/145818)	US	1/14/2003 (9/2/1998)	Method of fabricating a high power RF field effect transistor with reduced hot electron injection and resulting structure Xxxxxxxx Xxxxxx; Szehim Xxxxxx Xx
KR10-0633947 (KR10-2001-7002775)	KR	10/4/2006 (8/17/1999)	METHOD OF FABRICATING A HIGH POWER RF FIELD EFFECT TRANSISTOR WITH REDUCED HOT ELECTRON INJECTION AND RESULTING STRUCTURE Xxxxxx Xxxxxxxx; Ng Szehim Xxxxxx
6735422 (09/677975)	US	5/11/2004 (10/2/2000)	Calibrated DC compensation system for a wireless communication device configured in a zero intermediate frequency architecture Xxxxxxx, Xxxxx X.; Xxxxx, Xxxxxxx X.; Xxxxxxx, Xxxx X.; Xxxxxxx, X. Xxxxxxx; Xxxxxxxx, Xxxx X.
6674998 (09/747138)	US	1/6/2004 (12/21/2000)	System and method for detecting and correcting phase error between differential signals Xxxxxxxx, Xxxx X.
6891440 (09/747163)	US	5/10/2005 (12/21/2000)	Quadrature oscillator with phase error correction Xxxxxx, A. Xxxxxxx; Xxxxxxxx, Xxxx X.
6763228 (10/027386)	US	7/13/2004 (12/21/2001)	Precision automatic gain control circuit Xxxx X. Xxxxxxxx; Xxxxxxx X. Xxxxx
6748200 (10/407350)	US	6/8/2004 (4/4/2003)	Automatic gain control system and method for a ZIF architecture Xxxxxxx, Xxxx X.; Yeh, Xxxx X.; Xxxxxxx, Xxxxxx X.

RE42799 (12/147975)	US	10/4/2011 (6/27/2008)	Packet acquisition and channel tracking for a wireless communication device configured in a zero intermediate frequency architecture Xxxxx X. Xxxxxxx; Xxxx X. Xxxxxxx
6560448 (09/678901)	US	5/6/2003 (10/2/2000)	DC compensation system for a wireless communication device configured in a zero intermediate frequency architecture Xxxxx X. Xxxxxxx; Xxxxxxx X. Xxxxx; Xxxx X. Xxxxxxx; R. Xxxxxxx Xxxxxxx; Xxxx X. Xxxxxxxx
6448910 (09/818746)	US	9/10/2002 (3/26/2001)	METHOD AND APPARATUS FOR CONVOLUTION ENCODING AND VITERBI DECODING OF DATA THAT UTILIZE A CONFIGURABLE PROCESSOR TO CONFIGURE A PLURALITY OF RE-CONFIGURABLE PROCESSING ELEMENTS Xxxxxxxxx Xx
7127588 (09/730039)	US	10/24/2006 (12/5/2000)	Apparatus and method for an improved performance VLIW processor Mohamed, Xxxxxx X.; Xxxxxx, Xxxx X.
6757752 (10/043291)	US	6/29/2004 (1/14/2002)	Micro Controller Development System Xxx, Xxxx-Hong
6509646 (09/575637)	US	1/21/2003 (5/22/2000)	Apparatus For Reducing An Electrical Noise Inside A Ball Grid Array Package Xxx, Xxx-Feng; Xx, Xxxxx-Ju; Xxxx, Xxxx-Xxx
6365970 (09/458778)	US	4/2/2002 (12/10/1999)	Bond Pad Structure And Its Method Of Fabricating Tsai, Xxxx-Xxx; Xx, Xxxxx-Ju; Xxx, Xxx-Feng
6912601 (09/605325)	US	6/28/2005 (6/28/2000)	Method of programming PLDs using a wireless link Xxxxx, Xxxxxxx X.
6496054 (09/852185)	US	12/17/2002 (5/9/2001)	Control signal generator for an overvoltage-tolerant interface circuit on a low voltage process Xxxxxxx Xxxxx Xxxxxxx; Xxxxxxx Xxxxxxx Xxxxxxx
6194279 (09/340929)	US	2/27/2001 (6/28/1999)	Fabrication method for gate spacer Xxxx, Xxxx-Lung; Lin, Hsi-Chin; Hsiao, Hsi-Mao; Xxxxx, Xxx-Hua
6281554 (09/531905)	US	8/28/2001 (3/20/2000)	Electrostatic discharge protection circuit Xxx-Xxxxxx Pan
6657263 (09/896205)	US	12/2/2003 (6/28/2001)	MOS transistors having dual gates and self-aligned interconnect contact windows Ni, Xxxxx-Xxxxx
JP4846167 (JP2001-577605)	JP	10/21/2011 (4/3/2001)	Method of manufacturing a semiconductor device Xxxxx, Xxxxx X.; Woerlee, Xxxxxx X.; Knitel, Mathejs J.; Xxx Xxxxxxxxxxx, Xxxx C. M. C.
6461908 (09/829796)	US	10/8/2002 (4/10/2001)	Method of manufacturing a semiconductor device Xxxxx, Xxxxx Adriaan; Woerlee, Pierre Hermanus; Knitel, Mathijs Johan; Xxx Xxxxxxxxxxx, Xxxx Xxxxxxxxx Xxxxx Xxxxxxxx

0000000 (10/119545)	US	5/18/2004 (4/10/2002)	Clock and data recovery with a feedback loop to adjust the slice level of an input sampling circuit Xxxx Xxxxxxx Xxxxxx Xx.; Xxxxxxx Xxxx; Xxxxxxx Xxxxxx; Xxxxx Xxxxx Xx
6747522 (10/138027)	US	6/8/2004 (5/3/2002)	Digitally controlled crystal oscillator with integrated coarse and fine control Xxxxx X. Xxxxxxxxxxxxx; Xxxxxxx X. Xxxx
6275116 (09/328083)	US	8/14/2001 (6/8/1999)	METHOD, CIRCUIT AND/OR ARCHITECTURE TO IMPROVE THE FREQUENCY RANGE OF A VOLTAGE CONTROLLED OSCILLATOR Xxxxxxxx Xxxxxxxxxxx; Sung-Ki Min
6608763 (09/663753)	US	8/19/2003 (9/15/2000)	Stacking system and method Xxxxxx X. Xxxxx; Xxxxx X. Xxxxxx; Xxxxxx Xxxxxx
6404043 (09/598343)	US	6/11/2002 (6/21/2000)	Panel stacking of BGA devices to form three-dimensional modules Xxxxxx X. Xxxxx
6472735 (09/826621)	US	10/29/2002 (4/5/2001)	Three-dimensional memory stacking using anisotropic epoxy interconnections Xxxxxx X. Xxxxx
6544815 (09/922977)	US	4/8/2003 (8/6/2001)	Panel stacking of BGA devices to form three-dimensional modules Xxxxxx X. Xxxxx
6566746 (10/017553)	US	5/20/2003 (12/14/2001)	Panel stacking of BGA devices to form three-dimensional modules Xxxxxx X. Xxxxx; Xxxxxx X. Xxxx; Xxxx X. Xxxxxxx
6878571 (10/316566)	US	4/12/2005 (12/11/2002)	Panel stacking of BGA devices to form three-dimensional modules Xxxxxx X. Xxxxx; Xxxxxx X. Xxxx; Xxxx X. Xxxxxxx
6627984 (09/912010)	US	9/30/2003 (7/24/2001)	Chip stack with differing chip package types Xxx Xxxxx; Xxxx X. Xxxxxxx
6908792 (10/263859)	US	6/21/2005 (10/3/2002)	Chip stack with differing chip package types Xxx Xxxxx; Xxxx X. Xxxxxxx

EXHIBIT B

6205524 (09/153950)	US	3/20/2001 (9/16/1998)	MULTIMEDIA ARBITER AND METHOD USING FIXED ROUND-XXXXX SLOTS FOR REAL-TIME AGENTS AND A TIMED PRIORITY SLOT FOR NON-REAL-TIME AGENTS Xxxxx Xxx Ng
6157978 (09/226398)	US	12/5/2000 (1/6/1999)	MULTIMEDIA ROUND-XXXXX ARBITRATION WITH PHANTON SLOTS FOR SUPER-PRIORITY REAL-TIME AGENT Xxxxx Xxx Ng; Xxxxxx Xxxxxx Xxxxxx
6900654 (09/832884)	US	5/31/2005 (4/12/2001)	METHOD AND APPARATUS FOR EVALUATING A KNOWN GOOD DIE USING BOTH WIRE BOND AND FLIP-CHIP INTERCONNECTS Xxxxx X Xxxxxxxx; Xxxxxx Xxxx
CA2325232 (CA2325232)	CA	3/24/2009 (11/7/2000)	AN ELECTRICAL SENSING APPARATUS AND METHOD UTILIZING AN ARRAY OF TRANSDUCER ELEMENTS XXXXX-XXXXXX XXXX; XXX XXXX; XXXXXXXXXXX XXXXXX
EP00310686.1	EP	12/1/2000	Output stage for an array of electrical transducers XXXXXXXXXXX XXXXXX; XXXXX-XXXXXX XXXX; XXX XXXX
PCT/US2000/024770	WO	9/8/2000	LOW DIELECTRIC-CONSTANT ETCH STOP LAYER IN DUAL DAMASCENE PROCESS XXX XXXXX; XXXXX XXXXX
XX000000 (IN139/DEL/2001)	IN	10/17/2011 (2/9/2001)	Programmable Logic Device Including Bi-Directional Shift Register Ankur Bal
PCT/US2002/032230	WO	10/9/2002	MULTIPORT NON-BLOCKING HIGH CAPACITY ATM AND PACKET SWITCH Xxxxx Xxx; Xxxxx Xxxx; Jiu An; Xxxxxx X. Xxxxxx
XX0000000	CA	2/10/2000	Inductive Component, Integrated Transformer, Intended To Be Incorporated Into A Radio Frequency Circuit, And Integrated Circuit Associated With The Said Inductive Component Or Integrated Transformer XXXXX XXXX-XXXXXX; BASTERES LAURENT; MHANI AHMED; XXXXXXXX XXXXXXXX

EP00420039.0	EP	2/22/2000	Inductive Component, Integrated Transformer, In Particular For A Radio Frequency Circuit, And Associated Integrated Circuit With Such Inductive Component Or Integrated Transformer BASTERES LAURENT; XXXXX XXXX-XXXXXX; MHANI AHMED; XXXXXXXX XXXXXXXX
JP2000-047980	JP	2/24/2000	Inductor Element And Integrated Transformer Intended Particularly To Be Incorporated In High-Frequency Circuit, And Integrated Circuit Incorporating Such Inductor Element Or Integrated Circuit MHANI AHMED; XXXXXXXX XXXXXXXX; XXXXX XXXX-XXXXXX; BASTERES LAURENT
EP00420046.5	EP	3/21/2000	Monolithic Integrated Circuit Comprising An Inductor And A Method Of Fabricating The Same Xxxx-Xxxxxx Xxxxx; Ahmed Mhani; Laurent Basteres; Xxxxxxxx Xxxxxxxx
CA2301988	CA	3/22/2000	Monolithic Integrated Circuit With A Built-In Inductive Component And Procedure For Fabricating Such An Integrated Circuit Xxxx-Xxxxxx Xxxxx; Ahmed Mhani; Laurent Basteres; Xxxxxxxx Xxxxxxxx
JP2000-080808	JP	3/22/2000	Integrated Circuit With Incorporated Inductive Element And Manufacture Of The Same Xxxx-Xxxxxx Xxxxx; Ahmed Mhani; Laurent Basteres; Xxxxxxxx Xxxxxxxx
6548365 (10/177435)	US	4/15/2003 (6/21/2002)	Monolithic Integrated Circuit Incorporating An Inductive Component And Process For Fabricating Such An Integrated Circuit Xxxx-Xxxxxx Xxxxx; Ahmed Mhani; Laurent Basteres; Xxxxxxxx Xxxxxxxx
PCT/US1999/018780	WO	8/17/1999	METHOD OF FABRICATING A HIGH POWER RF FIELD EFFECT TRANSISTOR WITH REDUCED HOT ELECTRON INJECTION AND RESULTING STRUCTURE XXXXXX XXXXXXXX; NG SZEHIM XXXXXX
JP2000-569438	JP	8/17/1999	METHOD OF FABRICATING A HIGH POWER RF FIELD EFFECT TRANSISTOR WITH REDUCED HOT ELECTRON INJECTION AND RESULTING STRUCTURE Xxxxxx Xxxxxxxx; Ng Szehim Xxxxxx

EP99942284.3	EP	8/17/1999	METHOD OF FABRICATING A HIGH POWER RF FIELD EFFECT TRANSISTOR WITH REDUCED HOT ELECTRON INJECTION AND RESULTING STRUCTURE Xxxxxx Xxxxxxxx; Ng Szehim Xxxxxx
FR2773177 (FR9716631)	FR	3/17/2000 (12/29/1997)	PROCESS FOR OBTAINING A LAYER OF SINGLE CRYSTAL GERMANIUM OR SILICON ON SINGLE CRYSTAL SILICON OR GERMANIUM SUBSTRATE RESPECTIVELY, AND MULTILAYER PRODUCTS THUS OBTAINED XXXXXXXX XXXXXX; XXXXXXXXXX XXXX; XXXXXXXXX XXXXXXXX; XXXXXXX XXXXXXX
EP0930382 (EP98403096.5)	EP	8/21/2002 (12/9/1998)	PROCESS FOR OBTAINING A LAYER OF SINGLE CRYSTAL GERMANIUM OR SILICON ON SINGLE CRYSTAL SILICON OR GERMANIUM SUBSTRATE RESPECTIVELY, AND MULTILAYER PRODUCTS THUS OBTAINED XXXXXXXXXX XXXX; XXXXXXXXX XXXXXXXX; XXXXXXXX XXXXXX; XXXXXXX XXXXXXX
GB0930382 (GB98403096.5)	GB	8/21/2002 (12/9/1998)	PROCESS FOR OBTAINING A LAYER OF SINGLE CRYSTAL GERMANIUM OR SILICON ON SINGLE CRYSTAL SILICON OR GERMANIUM SUBSTRATE RESPECTIVELY, AND MULTILAYER PRODUCTS THUS OBTAINED XXXXXXXXXX XXXX; XXXXXXXXX XXXXXXXX; XXXXXXXX XXXXXX; XXXXXXX XXXXXXX
IT0930382 (IT502002901051938)	IT	8/21/2002 (12/9/1998)	PROCESS FOR OBTAINING A LAYER OF SINGLE CRYSTAL GERMANIUM OR SILICON ON SINGLE CRYSTAL SILICON OR GERMANIUM SUBSTRATE RESPECTIVELY, AND MULTILAYER PRODUCTS THUS OBTAINED XXXXXXXXXX XXXX; XXXXXXXXX XXXXXXXX; XXXXXXXX XXXXXX; XXXXXXX XXXXXXX
6117750 (09/217025)	US	9/12/2000 (12/21/1998)	Process for obtaining a layer of single-crystal germanium or silicon on a substrate of single-crystal silicon or germanium, respectively Xxxxxxx Xxxxxxx; Xxxxxx Xxxxxxxx; Xxxxxxxx Xxxxxxxxx; Xxxx Xxxxxxxxxx

6429098 (09/659913)	US	8/6/2002 (9/11/2000)	Process for obtaining a layer of single-crystal germanium or silicon on a substrate of single-crystal silicon or germanium, respectively, and multilayer products obtained Xxxxxx Xxxxxxxx; Xxxx Xxxxxxxxxx; Xxxxxxxx Xxxxxxxxx; Xxxxxxx Xxxxxxx
6134176 (09/199884)	US	10/17/2000 (11/24/1998)	DISABLING A DEFECTIVE ELEMENT IN AN INTEGRATED CIRCUIT DEVICE HAVING REDUNDANT ELEMENTS Xxxxxx X. Xxxxxxxxxx
60/259731	US	1/4/2001	Packet acquisition and channel tracking for a wireless communication device configured in a zero intermediate frequency architecture Xxxxx X. Xxxxxxx
7068987 (09/918409)	US	6/27/2006 (7/30/2001)	Packet acquisition and channel tracking for a wireless communication device configured in a zero intermediate frequency architecture Xxxxxxx, Xxxxx X.; Xxxxxxx, Xxxx X.
TWI178598 (TW090124159)	TW	6/1/2003 (9/28/2001)	A calibrated DC compensation system for a wireless communication device configured in a zero intermediate frequency architecture XXXXXXX XXXXX R; XXXXXXXX XXXX S; XXXXX XXXXXXX J; XXXXXXX R XXXXXXX; XXXXXXX XXXX A
PCT/US2001/030827	WO	10/1/2001	A calibrated DC compensation system for a wireless communication device configured in a zero intermediate frequency architecture Xxxxxxx, Xxxxx X.; Xxxxx, Xxxxxxx X.; Xxxxxxx, Xxxx X.; Xxxxxxx, X. Xxxxxxx; Xxxxxxxx, Xxxx X.
CN01819757.4	CN	10/1/2001	A calibrated DC compensation system for a wireless communication device configured in a zero intermediate frequency architecture Xxxxxxx, X. Xxxxxxx; Xxxxxxx, Xxxxx X.; Xxxxx, Xxxxxxx X.; Xxxxxxxx, Xxxx X.; Xxxxxxx, Xxxx X.
DE10196719.5	DE	10/1/2001	A calibrated DC compensation system for a wireless communication device configured in a zero intermediate frequency architecture Xxxxxxx, X. Xxxxxxx; Xxxxxxx, Xxxxx X.; Xxxxx, Xxxxxxx X.; Xxxxxxxx, Xxxx X.; Xxxxxxx, Xxxx X.
JP2002-533484	JP	10/1/2001	A calibrated DC compensation system for a wireless communication device configured in a zero intermediate frequency architecture Xxxxxxx, X. Xxxxxxx; Xxxxxxx, Xxxxx X.; Xxxxx, Xxxxxxx X.; Xxxxxxxx, Xxxx X.; Xxxxxxx, Xxxx X.

TWI173270 (TW090129833)	TW	3/11/2003 (12/3/2001)	System and method for detecting and correcting phase error between differential signals XXXXXXXX XXXX S
TWI175777 (TW090130645)	TW	4/21/2003 (12/11/2001)	Packet acquisition and channel tracking for a wireless communication device configured in a zero intermediate frequency architecture XXXXXXX XXXXX R; XXXXXXX XXXX A
PCT/US2001/049748	WO	12/20/2001	Quadrature oscillator with feedback phase mismatch correction Xxxxxx, A. Xxxxxxx; Xxxxxxxx, Xxxx X.
CN01821122.4	CN	12/20/2001	Quadrature oscillator with feedback phase mismatch correction Xxxxxx, A. Xxxxxxx; Xxxxxxxx, Xxxx X.
DE10197085.4	DE	12/20/2001	Quadrature oscillator with feedback phase mismatch correction Xxxxxx, A. Xxxxxxx; Xxxxxxxx, Xxxx X.
JP2002-566921	JP	12/20/2001	Quadrature oscillator with feedback phase mismatch correction Xxxxxx, A. Xxxxxxx; Xxxxxxxx, Xxxx X.
PCT/US2001/049751	WO	12/20/2001	Phase error detection and correction for differential signals Xxxxxxxx, Xxxx X.
CN01821282.4	CN	12/20/2001	System and method for detecting and correcting phase error between differential signals Xxxxxxxx, Xxxx X.
DE10197072.2	DE	12/20/2001	Phase error detection and correction for differential signals Xxxxxxxx, Xxxx X.
JP2002-552267	JP	12/20/2001	Phase error detection and correction for differential signals Xxxxxxxx, Xxxx X.
PCT/US2001/050268	WO	12/21/2001	Zero intermediate frequency receiver using package acquisition and channel tracking Xxxxxxx, Xxxxx X.; Xxxxxxx, Xxxx X.
CN01821763.X	CN	12/21/2001	Zero intermediate frequency receiver using information package to obtain channel tracking Xxxxxxx, Xxxxx X.; Xxxxxxx, Xxxx X.
DE10197148.6	DE	12/21/2001	Zero intermediate frequency receiver using package acquisition and channel tracking Xxxxxxx, Xxxxx X.; Xxxxxxx, Xxxx X.

JP2002-554982	JP	12/21/2001	Zero intermediate frequency receiver using package acquisition and channel tracking Xxxxxxx, Xxxxx X.; Xxxxxxx, Xxxx X.
KR10-2003-7009059	KR	12/21/2001	Zero intermediate frequency receiver using package acquisition and channel tracking Xxxxxxx, Xxxxx X.; Xxxxxxx, Xxxx X.
60/259295	US	1/2/2001	Precision automatic gain control circuit Xxxx X. Xxxxxxxx; Xxxxxxx X. Xxxxx
PCT/US2001/050599	WO	12/21/2001	Precision automatic gain control circuit Xxxx X. Xxxxxxxx; Xxxxxxx X. Xxxxx
TWI175258 (TW090132808)	TW	4/11/2003 (12/28/2001)	Precision automatic gain control circuit Xxxxx, Xxxxxxx X.; Xxxxxxxx, Xxxx X.
60/453905	US	3/11/2003	Automatic gain control system and method for a ZIF architecture Xxxxxxx, Xxxx X.; Yeh, Xxxx X.; Xxxxxxx, Xxxxxx X.
PCT/US2004/007408	WO	3/11/2004	Automatic gain control system and method for a ZIF architecture Xxxxxxx, Xxxx X.; Yeh, Xxxx X.; Xxxxxxx, Xxxxxx X.
TWI172580 (TW090124158)	TW	3/1/2003 (9/28/2001)	DC COMPENSATION SYSTEM FOR A WIRELESS COMMUNICATION DEVICE CONFIGURED IN A ZERO INTERMEDIATE FREQUENCY ARCHITECTURE Xxxxx X. Xxxxxxx; Xxxxxxx X. Xxxxx; Xxxx X. Xxxxxxx; R. Xxxxxxx Xxxxxxx; Xxxx X. Xxxxxxxx
PCT/US2001/042439	WO	10/1/2001	QUADRATURE DIRECT-CONVERSION DEMODULATOR USING DC OFFSET COMPENSATION Xxxxx X. Xxxxxxx; Xxxxxxx X. Xxxxx; Xxxx X. Xxxxxxx; R. Xxxxxxx Xxxxxxx; Xxxx X. Xxxxxxxx
CN01819755.8	CN	10/1/2001	QUADRATURE DIRECT-CONVERSION DEMODULATOR USING DC OFFSET COMPENSATION Xxxxxxx, Xxxxx X.; Xxxxx, Xxxxxxx X.; Xxxxxxx, Xxxx X.
DE10196720.9	DE	10/1/2001	A DC compensation system for a wireless communication device configured in a zero intermediate frequency architecture Xxxxxxx, Xxxxx X.; Xxxxx, Xxxxxxx X.; Xxxxxxx, Xxxx X.; Xxxxxxx, X. Xxxxxxx; Xxxxxxxx, Xxxx X.

JP2002-533468	JP	10/1/2001	A DC compensation system for a wireless communication device configured in a zero intermediate frequency architecture Xxxxxxx, Xxxxx X.; Xxxxx, Xxxxxxx X.; Xxxxxxx, Xxxx X.; Xxxxxxx, X. Xxxxxxx; Xxxxxxxx, Xxxx X.
6366998 (09/172315)	US	4/2/2002 (10/14/1998)	RECONFIGURABLE FUNCTIONAL UNITS FOR IMPLEMENTING A HYBRID VLIW-SIMD PROGRAMMING MODEL Mohamed, Xxxxxx X.
PCT/US1999/023039	WO	10/4/1999	RECONFIGURABLE FUNCTIONAL UNITS FOR IMPLEMENTING A HYBRID VLIW-SIMD PROGRAMMING MODEL Mohamed, Xxxxxx X.
EP01999878.0	EP	12/3/2001	A high performance VLIW processor Mohamed, Xxxxxx X.; Xxxxxx, Xxxx X.
EP97112557.0	EP	7/22/1997	Fault Recognition Method For Processor System Xxxxx, Xxxx; Xxxxxxxxxxxx, Xxxxx
DE19827431.9 (DE19827431.9)	DE	3/7/2001 (6/19/1998)	Fault Recognition Method For Processor System Xxxxx, Xxxx; Xxxxxxxxxxxx, Xxxxx
6401217 (09/120786)	US	6/4/2002 (7/22/1998)	Method for error recognition in a processor system Xxxxx, Xxxx; Xxxxxxxxxxxx, Xxxxx
KR10-0436051 (KR10-2001-0084263)	KR	6/3/2004 (12/24/2001)	Micro Controller Development System Xxx, Xxxx-Hong
6524942 (10/056004)	US	2/25/2003 (1/28/2002)	Bond Pad Structure And Its Method Of Fabricating Tsai, Xxxx-Xxx; Xx, Xxxxx-Ju; Xxx, Xxx-Feng
60/204423	US	5/13/2000	Bias generator circuit Xxxxxxx, X. Xxxxx; Xxxxxxx Xxxxxxx
60/204180	US	5/15/2000	Bias generator circuit Xxxxxxx, X. Xxxxx; Xxxxxxx Xxxxxxx
6169028 (09/237787)	US	1/2/2001 (1/26/1999)	Method for fabricating metal interconnected structure Xxxx, Xxx-Xxxx; Xxxx, Xxxx-Sheng; Xxxxx, Xxx-Yi
6190981 (09/243740)	US	2/20/2001 (2/3/1999)	Method for fabricating metal oxide semiconductor Xxx, Xxxx; Xxxx, Xxx-Xxx

XX000000 (TW088110425)	TW	3/21/2001 (6/22/1999)	Method for producing gate spacer capable of independent controlling the height and width of the spacer to be formed Xxxx, Xxx-Long; Lin, Xi-Chin; Xiao, Xi-Mao; Xxxxx, Xxx-Xxx
XXX000000 (TW088104775)	TW	5/1/2005 (3/26/1999)	Method for forming dual-gate MOS and interconnect with self-aligned contact Ni, Xxxxx-Xxxxx
6284578 (09/534699)	US	9/4/2001 (3/24/2000)	MOS transistors having dual gates and self-aligned interconnect contact windows Ni, Xxxxx-Xxxxx
6208004 (09/136482)	US	3/27/2001 (8/19/1998)	Semiconductor device with high-temperature-stable gate electrode for sub-micron applications and fabrication thereof Xxxxxxxxxx, Xxxxx X.
6479362 (09/783689)	US	11/12/2002 (2/14/2001)	Semiconductor device with high-temperature-stable gate electrode for sub-micron applications and fabrication thereof Xxxxxxxxxx, Xxxxx X.
EP00201317.5	EP	4/12/2000	HARD MASK FOR SEPARATING SOURCE/DRAIN AND POCKET IMPLANTS Xxxxx Xxxxx; Xxxxxx Xxxxxxx; Xxxxxxx Xxxxxxxx Xxxxxx; Xxxx Xxxxxxxxx
PCT/EP2001/003749	WO	4/3/2001	METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WOERLEE PIERRE H; VAN XXXXXXXXXXX XXXX C M C; XXXXX XXXXX A; KNITEL MATHIJS J
EP1275147 (EP01938077.3)	EP	6/24/2009 (4/3/2001)	HARD MASK FOR SEPARATING SOURCE/DRAIN AND POCKET IMPLANTS Xxxxx, Xxxxx X.; Woerlee, Xxxxxx X.; Knitel, Mathijs J.; Xxx Xxxxxxxxxxx, Xxxx C. M. C
DE60139068.7 (DE60139068.7)	DE	(4/3/2001)	HARD MASK FOR SEPARATING SOURCE/DRAIN AND POCKET IMPLANTS Xxxxx, Xxxxx X.; Woerlee, Xxxxxx X.; Knitel, Mathijs J.; Xxx Xxxxxxxxxxx, Xxxx C. M. C
FR1275147 (FR01938077.3)	FR	6/24/2009 (4/3/2001)	Method of manufacturing a semiconductor device Xxxxx, Xxxxx X.; Woerlee, Xxxxxx X.; Knitel, Mathijs J.; Xxx Xxxxxxxxxxx, Xxxx C. M. C
XX0000000 (GB01938077.3)	GB	6/24/2009 (4/3/2001)	Method of manufacturing a semiconductor device Xxxxx, Xxxxx X.; Woerlee, Xxxxxx X.; Knitel, Matheus J.; Xxx Xxxxxxxxxxx, Xxxx C. M. C.

KR10-0796825 (KR10-2001-7015928)	KR	1/15/2008 (4/3/2001)	Method of manufacturing a semiconductor device Xxxxx Xxxxx; Xxxxxx Xxxxxxx; Xxxxxxx Xxxxxxxx Xxxxxx; Xxxx Xxxxxxxxx
XXX000000 (TW090109425)	TW	5/21/2003 (4/19/2001)	Method of manufacturing a semiconductor device Xxxxx, Xxxxx X .; Woerlee, Xxxxxx X.; knitel, Mathijs J.; Xxx Xxxxxxxxxxx, Xxxx C. M. C.
6130823 (09/240623)	US	10/10/2000 (2/1/1999)	Stackable ball grid array module and method Xxxx X. Xxxxxx; Xxxxx X. Xxxx Xx.
PCT/US2001/010130	WO	3/29/2001	Panel stacking of BGA devices to form three-dimensional modules Xxxxxx X. Xxxxx
10/092073	US	3/6/2002	Three-dimensional memory stacking using anisotropic epoxy interconnections Xxxxxx X. Xxxxx
10/290994	US	11/8/2002	Panel stacking of BGA devices to form three-dimensional modules Xxxxxx X. Xxxxx
PCT/US2002/021546	WO	7/9/2002	Chip stack with differing chip package types Xxx Xxxxx; Xxxx X. Xxxxxxx

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