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EXHIBIT 10.17
*CERTAIN INFORMATION WITHIN THIS EXHIBIT HAS BEEN OMITTED AND THE NON-PUBLIC
INFORMATION HAS BEEN FILED SEPARATELY WITH THE SEC. CONFIDENTIAL TREATMENT HAS
BEEN REQUESTED WITH RESPECT TO THE OMITTED PORTIONS.
MEMORANDUM OF UNDERSTANDING
FOR
CUSTOM TOUCH(TM) 1T-SRAM(TM) MEMORY COMPILER
FOR TSMC 0.18um & 0.15um LOGIC PROCESSES
This Memorandum of Understanding (the "MOU") is entered into and effective as of
the date of the last signature below ("Effective Date") by and between Taiwan
Semiconductor Manufacturing Co., Ltd., a company duly incorporated under the
laws of the Republic of China ("ROC"), having its principal place of business at
Xx. 000, Xxxx Xxxxxx 0, Xxxxxxx Xxxxx Xxxxxxxxxx Xxxx, Xxxx-Xxx, Taiwan, ROC
("TSMC"), Monolithic System Technology Incorporated, a company duly incorporated
under the laws of the State of California, USA, having its principal place of
business at 0000 Xxxxxxx Xxxxx, Xxxxxxxxx, XX 00000 XXX ("MoSys"), and Virage
Logic Corporation, a company duly incorporated under the laws of the State of
California, USA, having its principal place of business at 00000 Xxxxxxx
Xxxxxxx, Xxxxxxx, XX 00000 XXX ("Virage").
PURPOSE
This MOU is to set forth parameters for an agreement for MoSys and Virage to
develop a Custom Touch(TM) 1T-SRAM(TM) memory compiler (the "Compiler") for
TSMC's 0.18um and 0.15um standard logic semiconductor processes to be jointly
marketed by all parties and sold to TSMC customers by MoSys and Virage.
TERM
This MOU is in place only as long as it takes the three parties to establish a
definitive agreement ("Definitive Agreement") covering the terms and conditions
of establishing and licensing the Compiler, but in no event longer that one (1)
year. TSMC may and licensing the Compiler, but in no event longer than one (1)
year. TSMC may terminate this MOU at any time in the event there is a
technological reason why the Compiler does not provide the functionality agree
to in the Compiler Statement of Work ("SOW") as defined herein.
Following the signature of this MOU, all parties shall use good faith and
reasonable efforts to conclude a definitive agreement within sixty (60) days of
the signature of this MOU.
CONSIDERATION
TSMC shall share the cost of the development of the Compiler with MoSys and
Virage in consideration for developing the Compiler for TSMC's 0.18um process
prior to any one else which would provide an advantage to TSMC and its customers
in the access to the
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Compiler. TSMC agree to pay ***, excluding any taxes and withholdings, for the
Development and the Compiler to MoSys and Virage jointly.
TSMC and MoSys shall amend the agreement executed between them dated March 31,
1999 to incorporate wafer-based running royalties for the compiled instances. It
is the intent of TSMC and MoSys to amend their agreement prior to the execution
of the Definitive Agreement.
TSMC and Virage agree that the Compiler and the resulting instances shall be
considered as "0.18um Licensed Products" and thus covered under TSMC's
Pay-for-Performance program as detailed in the Development and Licensing
Agreement executed between them on March 3, 1999.
In consideration for the cost sharing amount paid by TSMC, MoSys and Virage
agree to provide the Compiler for the 0.15um process to TSMC before any other
foundry customer so long as TSMC has provided the said process in a timely
manner. Such development shall be free of charge to TSMC from either MoSys or
Virage provided that at least five (5). TSMC 0.18um customers purchase the
Compiler from either MoSys and/or Virage for use in their chip development. TSMC
understands that the free of charge development of the Compiler for the 0.15 um
process does not necessarily mean no charge for future cost sharing of future
process generations.
PRODUCT
MoSys and Virage shall jointly develop the Compiler initially for TSMC's 0.18um
standard process that is not low voltage. The Compiler shall be developed in
accordance with the SOW which shall be agreed to by all parties, and shall be
updated from time to time by mutual agreement of all parties.
MoSys and Virage shall engineer the Compiler such that instances generated
include BIST, redundancy and fuse programming to ensure high yield and density.
MoSys and Virage shall provide the plans for all DFT planned such as BIST and
diagnostics.
The schedule for the Compiler development project shall be in accordance with
the SOW. The current date for the start of the development is intended to be two
weeks after receipt of cost sharing purchase order from TSMC. TSMC shall issue
the cost sharing purchase order to Virage in a timely manner from the date of
full execution of this MOU. The front-end view and GDS availability dates are to
be determined during the schedule development.
JOINT MARKET ACTIVITIES
TSMC, MoSys and Virage agree to perform joint marketing activities to promote
the relationship and the Compiler established by this MOU. Each entity shall be
financially responsible for its own marketing activities and such activities
must be pre-approved by
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the other two entities prior to launching such activities. The activities shall
include, but not be limited to, the following:
a) A joint press release that announces the established partnership and
planned Compiler, published after signature of this MOU by all
parties and the issuance of a purchase order for the cost sharing
amount by TSMC to MoSys and/or Virage;
b) Joint sales activities with TSMC by MoSys and Virage, to determine
customers for the Compiler;
c) Quarterly technology reviews to inform all parties of subsequent
technology developments that could lead to the modification of the
product established under this agreement, or to additional products
developed by and/or for the parties; and
d) Advertisement of the Compiler in the list of off-the-shelf
components by both MoSys and Virage, including published datasheets
to be used by both companies in the selling of the Compiler.
IN WITNESS WHEREOF, the parties hereto have caused this Agreement to be duly
executed in triplicate on their behalf by their duly authorized offers and
representatives on the date first given above.
TAIWAN SEMICONDUCTOR MANUFACTURING
CO., LTD.
/s/ XXXX XXXXXX
-----------------------------------
Xxxx Xxxxxx
Vice President, Corporate Marketing
MOSYS INCORPORATED VIRAGE LOGIC
CORPORATION
/s/ FU-XXXXX XXX /s/ XXXX XXXXXXXXX
----------------------------------- ---------------------------------------
Fu-Xxxxx Xxx Xxxx Xxxxxxxxx
Chairman, President & CEO President & CEO
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SOW#101999DSI_1
REVISION 1.0
OCTOBER 19, 1999
INTRODUCTION
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) is contracting with
Virage Logic Corporation (Virage) and MoSys, Inc. (MoSys) to construct a Custom
Touch(TM) 1T-SRAM(TM) Memory Compiler (1T Compiler) based on MoSys' 1T-SRAM(TM)
technology for TSMC's 0.18um standard process, under the business terms
delineated in the document, "Memorandum of Understanding For Custom Touch(TM)
1T-SRAM(TM) Memory Compiler for TSMC 0.18u and 0.15um Logic Processes." The
compilers to be constructed under this program are described in the Virage/MoSys
deliverables section, and are specified in the specification to be determined
and agreed upon by all parties. The work to be accomplished and schedule for
that work is delineated in the Microsoft Project document that shall be
submitted to TSMC by Virage and MoSys in a timely manner but no later than
thirty (30) days from the date of payment made by TSMC to Virage.
TSMC Deliverables
1. Approval of the Virage Logic/MoSys Custom Touch(TM) 1T-SRAM(TM) Memory
Compiler Specification, #MCPR-119, dated 9/28/99.
2. TSMC 0.18um process information to enable circuit simulation and GDS
layout.
3. TSMC personnel shall be available to answer technical questions pertaining
to the process technology by phone, fax, Email or in person.
Customer EDA Tool Flow
The following table describes TSMC's customer tool flow and EDA support
requirements for the purposes of deliverables under this SOW.
TOOL TYPE TOOL NAME TOOL VENDOR
------------- ---------------- ---------------
Simulation ModelSim Mentor Graphics
Simulation Verilog-XL Cadence
Synthesis Design Compiler Synopsys
Place & Route Apollo Avant!
Place & Route Silicon Ensemble Cadence
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Additional EDA views that are needed are to be developed in accordance with the
definitive contract signed between TSMC, MoSys and Virage for the 1T-SRAM
Program.
Virage/MoSys Deliverables
1. Project Schedule and design reviews as required
2. EDA Views to support the tool flow to include:
a) Verilog with SDF support
b) VHDL (VITAL) with SDF support
c) Test benches in Verilog and/or VHDL
d) Timing models in Synopsys .lib format
e) Structural netlists in Verilog and Spice
3. Physical and logical LEF
4. GDSII
5. Custom Touch(TM) 1T-SRAM(TM) Memory Compiler as described in the
specification #MCPR-119 attached in Appendix B.
REFERENCE DOCUMENTS
The following documents or the relevant information contained therein are the
entire reference basis for construction of the 1T compiler.
1. TSMC 0.18um Process Design Rules, Version XXX, Xxxxxxxx #XXX, TSMC, Ltd.
2. Virage Logic/MoSys Custom Touch(TM) 1T-SRAM(TM) Memory Specification,
Spec #MCPR-119, Virage Logic/MoSys, November 1, 1999.
3. Memorandum of Understanding For Custom Touch(TM) 1T SRAM(TM) Memory
Compiler for TSMC 0.18u & 0.15um Logic Processes, Version XXX, Xxxxxxxx
XXX, TSMC, Ltd.
4. Spice Model Version: Type: TBD, version TBD, 0.18um process.
WARRANTY
All Virage instances and compilers come with a 90-day warranty against defects.
To support changes in the process, we offer a foundry Maintenance option,
available for 20% of the list price of the compilers for 1 year of Maintenance.
Included is:
1. Extended warranty (1 year) for the Maintenance period.
2. 1 change in the design due to design rule changes.
3. Up to 3 recharacterizations due to changes in spice models or process
data.
4. Updated or new EDA models/views, as available.
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Pricing
Attachment A describes the pricing and payment schedule.
Delivery Schedule
The following memory compiler schedule is subject to a start date of 15 calendar
days after receipt of order.
ITEM #1 - Custom Touch(TM) 1T-SRAM(TM) Memory Compiler based on MoSys'
1T-SRAM(TM) technology for TSMC's 0.18um standard process as specified in Spec
#MCPR-119.
Milestone Date Deliverable
-------------- -----------
Milestone #0 - Project Start Final SOW
Milestone #1 - Start + 10 weeks Delivery of front end models
Milestone #2 - Start + 20 weeks Delivery of abstracts
Milestone #3 - Start + 24 weeks Delivery of final compiler with GDS
Virage Logic will conduct its customary quality assurance (QA) simulation and
testing.
Change Orders to SOW
Any party may request changes to any part of a previously agreed upon design
effort during the course of this SOW. Upon receipt of written request, the
receiving party shall promptly inform the other parties the acceptability,
effect and impact, if any, of the requested changes which shall include but is
not limited to, any change in price or scheduled completion dates. It is
understood that all work will continue as previously agreed and without regard
to the requested change until all parties have agreed in writing and have
amended the terms of this SOW accordingly.
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1. In the event that TSMC needs to update the specification of this
SOW, TSMC, MoSys and Virage Logic shall work together to plan
for the change in specification. TSMC shall have the option to
approve any increase in cost beforehand.
2. Addition/deletion to the SOW requires formal notification of all
parties with costs and schedule impact documented if possible.
3. Any changes to the original SOW requires a minimum of 2 weeks'
notice before the change can be initiated.
4. Any changes to the SOW will require re-confirmation of the
MoSys/Virage Logic deliverables schedule as well as the contents
of the deliverables.
5. Charge Order - Change orders are modifications required by TSMC
as a result of modifications to the original specification.
Written change orders will be acknowledged within one working
day upon receipt in writing or by email. MoSys/Virage Logic will
submit an initial estimate for the cost to complete the change
and any Schedule changes within 5 working days. MoSys/Virage
will also have the option to update the estimate within 15
working days of receipt of change order if any additional
discoveries are made that materially impact cost or schedule.
Please refer to the SOW number in all communications and purchase orders, as
applicable.
APPROVALS
The above statement of work and its attachments are understood and approved.
/s/ XXXX XXXXXX /s/ XXXX XXXXXXXXX /s/ FU-XXXXX XXX
--------------------------- -------------------------- -----------------
TSMC, Ltd. Virage Logic Corporation MoSys, Inc.
Xxxx Xxxxxx Xxxx Xxxxxxxxx Fu-Xxxxx Xxx
--------------------------- -------------------------- -----------------
Name Name Name
VP, Corp. Marketing President & CEO President
--------------------------- -------------------------- -----------------
Title Title Title
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Attachment A - Pricing
PRICE
TSMC shall pay *** to Virage Logic for the work specific in the MOU and
the SOW. Virage and MoSys agrees that such amount shall be shared equally
between Virage and MoSys.
Please refer to Quote dated October 19, 1999 previously submitted for accurate
pricing and terms information. The final quote will be attached to this section
for completeness, once an order for the subject compilers is received by Virage
Logic.
PAYMENT SCHEDULE
The payment schedule is milestone based, with percentages due based on the work
completed for that milestone. The milestone numbering is consistent with the
product deliveries.
Milestone #0 - Project Start, Delivery of Final SOW - 30% of total order amount
Milestone #1 - Delivery of front end models - 25% of total order amount
Milestone #2 - Delivery of abstracts - 20% of total order amount
Milestone #3 - Final compiler version delivery - 25% of total order amount
PAYMENT TERMS
Payment terms are net 30.
