Exhibit 4.1
AMENDMENT TO SECURITY AGREEMENT
AND
RELEASE OF CERTAIN INTELLECTUAL PROPERTY
This Amendment and Release ("Amendment") to the Security Agreement dated as of
March 28, 2002 (the "Security Agreement") by and between Infineon Technologies
AG, a German stock corporation ("Infineon"), and Ramtron International
Corporation, a Delaware corporation (the "Company") is dated as of March 30,
2004, and is being entered into by and between Infineon and the Company.
RECITALS
WHEREAS, Infineon and the Company entered into the Security Agreement in order
to provide Infineon with a security interest in and to all of the Company's
right, title and interest in and to the Collateral to secure the Company's
repayment obligations under the Debenture purchased by Infineon pursuant to the
Securities Purchase Agreement;
WHEREAS, pursuant to the Waiver Agreement dated August 18, 2003, by and between
Infineon and the Company (the "Waiver Agreement"), the Company has agreed to
make certain Waiver Payments (as defined in the Waiver Agreement) to decrease
the Company's indebtedness under the Debenture;
WHEREAS, the Company wishes to sell the "Released IP" (as defined below) and
within two business days after Company's receipt of proceeds from the sale of
the Released IP, the Company will pay (by wire transfer or other agreed method)
to Infineon the amount of On million ninety thousand Dollars ($1,090,000.00)
or, if less, the full amount the Company receives as consideration for its sale
of the Released IP (the "Payment"), which Payment shall, up to the amount of
such Payment, (i) satisfy and be conclusively deemed to be in lieu of the
Waiver Payments provided in Section 2 of the Waiver Agreement, and (ii) reduce
the amount due under the Debenture Dollar for Dollar; the reminder, if any, of
the Waiver Payments and the Debenture shall being due and payable in accordance
with the agreed time schedules; and concurrently herewith, Infineon will
release certain Collateral under the Security Agreement; and
WHEREAS, in consideration of the Payment to be made by the Company to Infineon,
Infineon and the Company hereby wish to amend the Security Agreement and to
execute a Release to delete from the Collateral certain intellectual property
("Released IP") listed on Schedule "1" as attached hereto.
NOW, THEREFORE, in consideration of the foregoing recitals, the following
covenants and promises and other good and valuable consideration, the receipt
and sufficiency of which are hereby acknowledged, the parties hereto hereby
agree as follows:
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1. Definitions
Unless otherwise defined herein, all capitalized terms used herein and not
otherwise defined herein shall have the respective meanings set forth in the
Security Agreement, and references to "Section" or "Sections" herein are
references to the specified sections of the Security Agreement.
2. Amendment
Section 1 - "Grant of Security". Section 1 of the Security Agreement is
amended and restated to exclude the Released IP from the definition of
Collateral.
3. Release
In consideration of and subject to the Payment to be made by the Company to
Infineon under the Debenture and for other good and valuable consideration, the
receipt and sufficiency of which are hereby acknowledged, Infineon has RELEASED
and DISCHARGED, and by these presents does RELEASE and DISCHARGE, the Released
IP from any and all security interests and liens held by Infineon and securing
any indebtedness of the Company to Infineon and does hereby reassign and vest
in the Company full title to the Released IP assigned to Infineon under the
Security Agreement.
4. Effect of Amendment
Except as expressly modified by the provisions of this Amendment, the Security
Agreement and all of the terms, provisions and conditions thereof shall for all
purposes remain unchanged, and in full force and effect, and are approved,
ratified and confirmed, and from and after the date hereof all references to
the Agreement in any other agreement to which any of the undersigned are
parties shall mean the Agreement as amended hereby. Without limiting the
foregoing, Infineon and the Company agree that nothing herein affects in any
way any license or other rights of Infineon in and to the Released IP, other
than the security interest released in this Amendment.
5. UCC3 Filing
Infineon hereby authorizes the Company to file an amendment to UCC financing
statement No. 2076971 5, filed on April 23, 2002, against the Company (the
"Original Financing Statement"), with the Secretary of State of the State of
Delaware, to delete the Released IP from the collateral listed on the Original
Financing Statement.
6. Counterparts
This Amendment may be executed in any number of counterparts, each of which
will be deemed an original, but all of which together will constitute one and
the same instrument.
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IN WITNESS WHEREOF, the parties hereto have executed this Amendment effective
as of the date set forth in the preamble hereof.
INFINEON TECHNOLOGIES AG RAMTRON INTERNATIONAL CORPORATION
By /S/ Xxxxx Xxxxxxxxxxx By /S/ XxXxx X. Xxxxxx
----------------------------- --------------------------
Name: Xxxxx Xxxxxxxxxxx Name: XxXxx X. Xxxxxx
Title: VP Business Dev. Title: Chief Financial Officer
By /S/ Xxxxx Xxxxx
------------------------
Name: Xxxxx Xxxxx
Title: Corp. Legal Counsel
Page-3
Schedule "1"
RELEASED IP
Patent or Title
Application No. Country Filing Date Inventors
--------------- ------- ----------- -----------------------------------
Xxx. 5,104,822 U.S. 07/30/1990 Method For Creating Self-Aligned,
(RAM 317) Non-Patterned Contact Areas And
Stacked Capacitors Using The
Method
Xxxxxx
-----------------------------------------------------------------------------
Xxx. 5,162,890 U.S. 04/05/1991 Stacked Capacitor With Sidewall
(RAM 317 DIV) Insulation
Xxxxxx
------------------------------------------------------------------------------
Xxx. 0000000 Xxxxx 07/30/1991 Method For Creating Self-Aligned,
(RAM 317 JPN) Non-Patterned Contact Areas And
Stacked Capacitors Using The
Method
Xxxxxx
------------------------------------------------------------------------------
Xxx. 5,170,242 U.S. 05/10/1991 Reaction Barrier For A Multilayer
(RAM 319 CON) Structure In An Integrated Circuit
Xxxxxxx, Maekawa
------------------------------------------------------------------------------
Xxx. 0000000 Xxxxx 07/13/1990 Reaction Barrier For A Multilayer
(RAM 319 JPN) Structure In An Integrated Circuit
Xxxxxxx, Maekawa
------------------------------------------------------------------------------
Xxx. 5,075,817 U.S. 6/22/1990 Trench Capacitor For Large Scale
(RAM 320) Integrated Memory
Xxxxxx
-------------------------------------------------------------------------------
Xxx. 0000000 Xxxxx 06/21/1991 Trench Capacitor For Large Scale
(RAM 320 JPN) Integrated Memory
Xxxxxx
-------------------------------------------------------------------------------
Xxx. 5,610,099 U.S. 06/28/1994 Process For Fabricating
(RAM 321) Transistors Using Composite
Nitride Structure
Stevens, Bailey, Xxxxxx
------------------------------------------------------------------------------
Page-4
Xxx. 5,043,790 U.S. 04/05/1990 Sealed Self Aligned Contacts Using
(RAM 322) Two Nitrides Process
Xxxxxx
------------------------------------------------------------------------------
Xxx. 5,216,281 U.S. 08/26/1991 Sealed Self Aligned Contact
(RAM 322 CIP) Incorporating A Dopant Source
Xxxxxx
------------------------------------------------------------------------------
Xxx. 0000000 Xxxxx 04/05/1991 Sealed Self Aligned Contacts Using
(RAM 322 JPN) Two Nitrides Process
Xxxxxx
------------------------------------------------------------------------------
Xxx. 5,134,310 U.S. 01/23/1991 Current Supply Circuit For
(RAM 324) Driving High Capacitance Load In
An Integrated Circuit
Xxxxxx, Xxxxx
------------------------------------------------------------------------------
Xxx. 0000000 Xxxxx 01/23/1992 Current Supply Circuit For
(RAM 324 JPN) Driving High Capacitance
Load In An Integrated Circuit
Xxxxxx, Xxxxx
------------------------------------------------------------------------------
Xxx. 5,117,177 U.S. 01/23/1991 Reference Generator For An
(RAM 325) Integrated Circuit
Xxxxx
------------------------------------------------------------------------------
Xxx. 0000000 Xxxxx 01/23/1992 Reference Generator For An
(RAM 325 JPN) Integrated Circuit
Xxxxx
------------------------------------------------------------------------------
Xxx. 5,255,222 U.S. 01/23/1991 Output Control Circuit Having
(RAM 326) Continuously Variable Drive
Current
Xxxxx
-------------------------------------------------------------------------------
Xxx. 0000000 Xxxxx 01/22/1992 Output Control Circuit Having
(RAM 326 JPN) Continuously Variable Drive
Current
Xxxxx
------------------------------------------------------------------------------
Page-5
Xxx. 5,699,317 U.S. 10/06/1994 Enhanced Dram With All Reads
(RAM 343 CIP) From On-Chip Cache And All Writes
To Memory Array
Mobley, Sartore, Xxxxxxxx, Xxxxx
------------------------------------------------------------------------------
Xxx. 5,721,862 U.S. 06/02/1995 Enhanced Dram With Single Row
(RAM 343 CON) SRAM Cache For All Device Read
Operations
Mobley, Sartore, Xxxxxxxx, Xxxxx
------------------------------------------------------------------------------
Xxx. 69324508.5 Germany 01/14/1993 Edram With Embedded Registers
(RAM 343 DE)
Mobley, Sartore, Xxxxxxxx, Xxxxx
------------------------------------------------------------------------------
Xxx. 5,887,272 U.S. 07/03/1997 Enhanced Dram With Embedded
(RAM 343 DIV) Registers
Mobley, Sartore, Xxxxxxxx, Xxxxx
------------------------------------------------------------------------------
Xxx. 6,347,357 U.S. 10/30/1998 Enhanced Dram With Embedded
(RAM 343 DIV/CON) Registers
Mobley, Sartore, Xxxxxxxx, Xxxxx
------------------------------------------------------------------------------
App. 09/962,287 U.S. 09/24/2001 Enhanced Dram With Embedded
(RAM 343 DIV/CON2) Registers
Mobley, Sartore, Xxxxxxxx, Xxxxx
------------------------------------------------------------------------------
Xxx. 0000000 Xxxxx 01/21/1993 EDRAM Having A Dynamically-Sized
(RAM 343 JPN) Cache Memory And Associated Method
Mobley, Sartore, Xxxxxxxx, Xxxxx
------------------------------------------------------------------------------
Xxx. 5,566,318 U.S. 08/02/1994 Circuit With A Single Address
(RAM 381) Register That Augments A Memory
Controller By Enabling Cache
Reads And Page-Mode Writes
Xxxxxx
------------------------------------------------------------------------------
Xxx. 5,835,442 U.S. 03/22/1996 EDRAM With Integrated Generation
(RAM 393) And Control Of Write Enable And
Column Latch Signals And Method
For Making Same
Xxxxxx, X.X. Xxxxxxx, X.X. Xxxxxxx
------------------------------------------------------------------------------
Page-6
Xxx. 5,991,851 U.S. 05/02/1997 Enhanced Signal Processing Random
(RAM 417) Access Memory Device Utilizing A
Dram Memory Array Integrated With
An Associated SRAM Cache And
Internal Refresh Control
Alwais, Xxxxxx
------------------------------------------------------------------------------
Xxx. 5,901,100 U.S. 04/01/1997 First-In, First-Out Integrated
(RAM 418) Circuit Memory Device Utilizing
A Dynamic Random Access Memory
Array For Data Storage Implemented
In Conjunction With An Associated
Static Random Access Memory Cache
Xxxxxx
------------------------------------------------------------------------------
Xxx. 6,072,741 U.S. 03/11/1999 First-In, First-Out Integrated
(RAM 418 CIP) Circuit Memory Device Utilizing A
Dynamic Random Access Memory Array
For Data Storage Implemented In
Conjunction With An Associated
Static Random Access Memory Cache
Xxxxxx
------------------------------------------------------------------------------
Xxx. 6,172,927 U.S. 03/24/2000 First-In, First-Out Integrated
(RAM 418 CIP2) Circuit Memory Device
Incorporating A Retransmit
Function
Xxxxxx
------------------------------------------------------------------------------
Xxx. 6,141,281 U.S. 04/29/1998 Technique For Reducing Element
(RAM 429) Disable Fuse Pitch Requirements In
An Integrated Circuit Device
Incorporating Replaceable Circuit
Elements
Xxxxxx, Ash
------------------------------------------------------------------------------
Xxx. 6,055,192 U.S. 09/03/1998 Dynamic Random Access Memory
(RAM 430) Word Line Boost Technique
Employing A Boost-On-Writes Policy
Xxxxxx
------------------------------------------------------------------------------
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Xxx. 6,064,620 U.S. 07/08/1998 Multi-Array Memory Device, And
(RAM 432) Associated Method, Having Shared
Decoder Circuitry
Xxxxxx
-------------------------------------------------------------------------------
Xxx. 6,278,646 U.S. 03/23/2000 Multi-Array Memory Device And
(RAM 432 CIP) Associated Method Having Shared
Decoder Circuitry
Xxxxxx
-------------------------------------------------------------------------------
Xxx. 5,963,481 U.S. 06/30/1998 Embedded Enhanced DRAM And
(RAM 447) Associated Method
Alwais, Xxxxxx
-------------------------------------------------------------------------------
App. 99302956.0 Europe 04/16/1999 Embedded Enhanced DRAM And
(RAM 447 EPO) Associated Method
Alwais, Xxxxxx
-------------------------------------------------------------------------------
Xxx. 6,249,840 U.S. 10/23/1998 Multi-Bank Esdram With Cross-
(RAM 448) Coupled SRAM Cache Registers
Xxxxxx
------------------------------------------------------------------------------
Xxx. 6,330,636 U.S. 01/25/1999 Double Data Rate Synchronous
(RAM 450) Dynamic Random Access Memory
Device Incorporating A Static
RAM Cache Per Memory Bank
Bondurant, Peters, Xxxxxx
------------------------------------------------------------------------------
Xxx. 6,151,236 U.S. 02/29/2000 Enhanced Bus Turnaround Integrated
(RAM 460) Circuit Dynamic Random Access
Memory Device
Bondurant, Fisch, Grieshaber,
Mobley, Xxxxxx
------------------------------------------------------------------------------
Xxx. 6,301,183 U.S. 07/27/2000 Enhanced Bus Turnaround Integrated
(RAM 460 CON) Circuit Dynamic Random Access
Memory Device
Bondurant, Fisch, Grieshaber,
Mobley, Xxxxxx
------------------------------------------------------------------------------
Page-8
App. 2001-052888 Japan 02/27/2001 Enhanced Bus Turnaround Integrated
(RAM 460 JPN) Circuit Dynamic Random Access
Memory Device
Bondurant, Fisch, Grieshaber,
Mobley, Xxxxxx
------------------------------------------------------------------------------
Xxx. 6,392,441 U.S. 06/13/2000 Fast Response Circuit
(RAM 461)
Moscaluk
------------------------------------------------------------------------------
Xxx. 6,373,751 U.S. 05/15/2000 Packet-Based Integrated Circuit
(RAM 463) Dynamic Random Access Memory
Device Incorporating An On-Chip
Row Register Cache To Reduce Data
Access Latencies
Bondurant
------------------------------------------------------------------------------
Xxx. 6,549,472 U.S. 02/21/2002 Packet-Based Integrated Circuit
(RAM 463 CON) Dynamic Random Access Memory
Device Incorporating An On-Chip
Row Register Cache To Reduce Data
Access Latencies
Bondurant
------------------------------------------------------------------------------
Xxx. 6,646,928 U.S. 01/16/2003 Packet-Based Integrated Circuit
(RAM 463 DIV) Dynamic Random Access Memory
Device Incorporating An On-Chip
Row Register Cache To Reduce Data
Access Latencies
Xxxxxxxxx
-------------------------------------------------------------------------------
Xxx. 6,501,698 U.S. 11/01/2000 Structure And Method For Hiding
(RAM 464) DRAM Cycle Time Behind A Burst
Access
Xxxxxx
------------------------------------------------------------------------------
App. 09/828,283 U.S. 04/05/2001 Method For Hiding A Refresh In
(RAM 465) A Pseudo-Static Memory
Xxxxxx
------------------------------------------------------------------------------
Xxx. 6,538,928 U.S. 10/11/2000 Method For Reducing The Width
(RAM 468) Of A Global Data Bus In A Memory
Architecture
Xxxxxx
------------------------------------------------------------------------------
Page-9
App. 09/828,488 U.S. 04/05/2001 Method And Circuit For Increasing
(RAM 487) The Memory Access Speed Of An
App. 10/782,386 02/18/2004 Enhanced Synchronous SDRAM
(RAM 487 CON)
Xxxxxx
------------------------------------------------------------------------------
App. 10/178,072 U.S. 06/20/2002 Method And Circuit For Increasing
(RAM 491) The Memory Access Speed Of An
Enhanced Synchronous SDRAM
Mobley, Peters, Xxxxxxxx
------------------------------------------------------------------------------
Xxx. 5,787,457 U.S. 10/18/1996 Cached Synchronous DRAM
Architecture Allowing Concurrent
DRAM Operations
Miller, Rogers, Tomashot,
Bondurant, Jones, Jr., Xxxxxx
------------------------------------------------------------------------------
Xxx. 6,289,416 U.S. 10/15/1999 Cached Synchronous DRAM
Architecture Having A Mode
Register Programmable Cache Policy
Rogers, Tomashot, Bondurant,
Jones, Jr., Xxxxxx
------------------------------------------------------------------------------
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