EXHIBIT 10.8.2
[XXXXXX]=CERTAIN INFORMATION ON THIS PAGE HAS BEEN OMITTED PURSUANT TO AN ORDER
GRANTING CONFIDENTIAL TREATMENT ISSUED BY THE SECURITIES AND EXCHANGE COMMISSION
FIRST ADDENDUM TO
JOINT DEVELOPMENT AND LICENSE AGREEMENT
THIS IS A FIRST ADDENDUM TO THAT CERTAIN JOINT DEVELOPMENT AND LICENSE AGREEMENT
DATED AUGUST 20, 1993, (the "Original Agreement") among Nintendo Co., Ltd.
("NCL"), Nintendo of America Inc. ("NOA")(NCL and NOA are collectively referred
to as "Company"), Silicon Graphics, Inc., and MIPS Technologies, Inc.
(collectively referred to as "SGI").
NOW, THEREFORE, the parties hereby agree as follows:
1. DEFINITIONS. THE DEFINITIONS IN THE ORIGINAL AGREEMENT ARE HEREBY
incorporated by reference in this FIRST ADDENDUM.
2. BUDGET. SGI HAS ADVISED THE COMPANY THAT THE BUDGET FOR SGI'S WORK UNDER THE
Development Plan is U.S. XXXXXXXXX (the "Budget"). The Budget represents SGI's
good faith calculation of its actual costs to complete its work under the
Development Plan which includes, but is not limited to, SGI's costs of personnel
resources, equipment costs for experimentation, development and CAD tools. The
Budget is stated as a flat fee (fixed fee) for the completion of SGI's work
under the Development Plan. Company hereby accepts the Budget and shall make
payment to SGI in accordance with Schedule B. SGI acknowledges that the Company
has already paid U.S. XXXXXXXXX of the Budget.
3. DEVELOPMENT PLAN. THE PARTIES AGREE TO THE DEVELOPMENT PLAN SET FORTH ON
Schedule A. The parties acknowledge that Section 4.4 of the Original Agreement
requires that the parties use "reasonable efforts" to develop the Developed
Technology substantially in accordance with the Development Plan attached as
Schedule A, or any revised Development Plan agreed upon by the parties,
including any applicable target dates.
Except as set forth herein, the Original Agreement is hereby ratified and
confirmed.
NINTENDO CO., LTD. NINTENDO OF AMERICA INC.
By: /s/ Xxxxxxx Xxxxxxxx By: /s/ Xxxxxx Xxxxxxx
-------------------- ------------------
Mr. Xxxxxxx Xxxxxxxx Xx. Xxxxxx Xxxxxxx
President President
February 4, 1994 February 5th, 1994
SILICON GRAPHICS, INC. MIPS TECHNOLOGIES, INC.
By: /s/ Xxx Xxx BY: /s/ Xxx Xxx
----------- -----------
Name: Xxx Xxx Name: Xxx Xxx
Title: Senior Vice President Title: Chairman of the Board
February 4 , 1994 February 4 , 1994
Attachments: Schedules A, A-1, and B.
FINAL: 2-3-94
SCHEDULE A
DEVELOPMENT PLAN
OBJECTIVES:
The objectives under this Development Plan are to develop and design:
1. Consumer Hardware that: (a) will have SGI-Class Graphics Performance (see
definition below) and other specifications to be identified by the parties, (b)
has a target date of September 1, 1995 for commercial shipment by Company to its
retailers and dealers so that Company can sell the Consumer Hardware during the
1995 holiday season, and (c) has a suggested retail price of U.S. $250 or less.
2. Coin-Operated Hardware, which will use an enhanced and/or modified version
of the Consumer Hardware LSI chip set, the specifications for which are to be
identified by the parties by mutual agreement.
3. Initial Emulation Unit(s) (defined herein) and its video game development
environments, which will allow the Company and a relatively small number of its
video game developers to proceed as quickly as possible to create exciting video
games (prior to the time that the Licensee Emulation Unit is available) so that
video games playable on the Consumer Hardware are ready for commercial shipment
simultaneously with the commercial shipment of the Consumer Hardware in order to
support a strong launch of the Consumer Hardware.
4. a Licensee Emulation Unit (defined herein) and its video game development
environments, which will be available to Company and its licensees in order to
create exciting video games playable on the Consumer Hardware.
PARTIES' TASKS:
1. LSI (LARQE SCALE INTEGRATED CIRCUIT) DESIGN FOR CONSUMER HARDWARE.
A. DESCRIPTION: SGI shall be responsible for the LSI (Large Scale Integrated
circuit) design for the Consumer Hardware, which includes LSI's verification,
cost-conscious, testability, and reliability design for critical- mass
semiconductor production. The Consumer Hardware is expected to have SGI- Class
Graphics Performance, the current target specifications for which are set forth
in Schedule A1 (called Home Box Baseline), which target specifications set forth
the functionality of a hyper 2D application. SGI and Company acknowledge that
they will mutually agree on modifications and/or additions to the target
specifications in the Home Box Baseline to achieve the functionality of an
integrated architecture that is capable of both hyper 2D and 3D graphics for
video games. SGI and Company also acknowledge that, by mutual agreement, they
will modify functional specifications based on the affect of various functional
alternatives on the suggested retail price for the Consumer Hardware, the
desirability of the Consumer Hardware to the market, and the target dates set
forth in this Development Plan. The parties will jointly agree and approve the
final design for the LSI chip set. The parties do not know the number of LSI
chips to be designed but consider the range to be from two (2) to three (3)
chips. Company contemplates that it will designate one company (NEC) to be the
only vendor for the LSI chip set until the first commercial shipment by Company
of the Consumer Hardware. Therefore, for purposes of this Development Plan, SGI
will be obligated to work with only one vendor of the LSI chip set. The
following are the function blocks to be included in the chip(s):
(i) CENTRAL PROCESSING UNIT ("CPU").
[XXXXXX]=CERTAIN INFORMATION ON THIS PAGE HAS BEEN OMITTED PURSUANT TO AN
ORDER GRANTING CONFIDENTIAL TREATMENT ISSUED BY THE SECURITIES AND EXCHANGE
COMMISSION.
DESCRIPTION: The parties contemplate that the CPU will be a MIPS R4000 series or
a derivative. If any customization is necessary, it will be done by SGI, in
consultation with Company and the CPU vendor selected by Company. The
customization, if any, would remove unnecessary functions from the CPU, and add
additional functions desirable for video games including, but without
limitation, security microcode for curbing counterfeiting of video games.
(ii) GRAPHIC AND/OR AUDIO DIGITAL SIGNAL PROCESSOR ("DSP")
DESCRIPTION: Programmable DSP which provides graphic geometry calculation and
other arithmetic calculations and/or sound signal generation, which will be
tuned with the CPU for maximum performance within the price considerations.
(iii) GRAPHIC DRAWING ENGINE ("GDE").
DESCRIPTION: The GDE shall have SGI-Class Graphics Performance and other
specifications to be identified by the parties (including Company's
specifications relevant to video gaming).
(iv) DYNAMIC RANDOM ACCESS MEMORY ("DRAM") DEVICES. DESCRIPTION: The Consumer
Hardware shall include an architecture for efficient utilization of dynamic
random access memory ("DRAM") devices.
(v) INPUT/OUTPUT ("I/O"). DESCRIPTION: Input from game controller, joystick,
microphone, etc. and interface to game storage device (ROM cartridge, CD ROM,
etc.), output to sound DAC (Digital to Analog Converter), output to video DAC
for a variety of video output standards, input and output with expansion port,
and input and output with communication port. The parties contemplate that the
I/O interface will be integrated into the LSI chip set.
B. DELIVERABLES AND TARGET DATES.
(i) SGI Deliverable for the LSI chip set: First silicon. A block diagram and
technical documentation related to the design of the LSI chip set delivered by
SGI to the Company.
(ii) Target Dates:
(a) Desirable Target Date for first silicon: January 1, 1995.
(b) Latest Target Date for first silicon: March 31, 1995.
(c) Desirable Target Date for finalizing the choice of DRAM: February 5, 1994.
(d) Latest Target Date for finalizing the choice of DRAM: March 15, 1994.
C. PAYMENT TO THIRD PARTY: To the extent any payment is required to be paid to
a third party for the LSI chip set, at SGI's expense, SGI shall be responsible
for making such payment (in an amount not to exceed U.S. XXXXXX
2. ENHANCED AND/OR MODIFIED VERSION OF LSI DESIGN FOR COIN-OPERATED HARDWARE.
DESCRIPTION: SGI shall be responsible for the enhancement of and/or modification
to the Consumer Hardware LSI for the Coin-Operated Hardware LSI. The parties
will meet and agree on the appropriate revisions/modifications. The target date
for meeting and reaching agreement on the appropriate revisions/modifications is
First Quarter 1994. The parties will jointly agree and approve the final design
for the enhanced LSI for the Coin-Operated Hardware.
SGI DELIVERABLE: First silicon of enhanced Consumer Hardware LSI. A block
diagram and technical documentation for the LSI chip set to be delivered by SGI
to Company.
DESIRABLE TARGET DATE FOR SGI DELIVERABLE: To be agreed.
LATEST TARGET DATE FOR SGI DELIVERABLE: To be agreed.
3. ENGINEERING WORK/TECHNICAL INVESTIGATIONS.
DESCRIPTION: Although Company shall be responsible for the design and
engineering of the Consumer Hardware and Coin-Operated Hardware through use of
SGl's LSI chip set, upon the request of Company, SGI shall provide reasonable
assistance to the Company in this process including, but without limitation, by
SGI making reasonable technical investigations for assessing the feasibility of
engineering options (e.g. investigating choice of components), and by assisting
the Company with the design and engineering of the Consumer Hardware and
Coin-Operated Hardware (e.g. designing PC board artwork, FCC countermeasures,
expandability through add-ons like an CD ROM adapter). In addition, to the
extent there is a design-originated "bug" that occurs after the parties jointly
approve the final LSI chip set, SGI will provide technical advice on how to
correct the problem.
SGI DELIVERABLE: Depends on the request made by the Company.
TARGET DATE FOR SGI DELIVERABLE: For the Consumer Hardware, SGI's assistance
will be on-going until the first commercial shipment of the Consumer Hardware or
final approval of the LSI chip set for the Consumer Hardware, whichever occurs
later. For the Coin-Operated Hardware, SGI's assistance with be on-going until
the parties jointly approve the final LSI design for the Coin-Operated Hardware.
4. INITIAL EMULATION UNITS.
DESCRIPTION: SGI shall be responsible for the design of emulation units of the
Consumer Hardware (the "Initial Emulation Units"), which shall consist of the
(i) First Initial Emulation Unit, and (ii) the Second Initial Emulation Unit.
The Initial Emulation Units shall be designed according to the specifications
agreed to by SGI and Company. The Initial Emulation Units will be used by the
Company and its video game developers to develop initial games for play on the
Consumer Hardware.
FIRST INITIAL EMULATION UNIT.
The parties contemplate that the First Initial Emulation Unit will consist of a
high-performance SGI system (e.g. the Reality Engine) and software which will
closely represent the functionality of the Consumer Hardware. The parties agree
that it is important that the First Initial Emulation Unit provide a realistic
"look and feel" of the Consumer Hardware to be designed and have the approximate
clocktime of the Consumer Hardware to be designed. The parties contemplate that
SGl's tasks for the First Initial Emulation Unit will include the following: (i)
if interface hardware is necessary, implementation for a small production (10 -
20 units) of interface hardware, (ii) development of software for the First
Initial Emulation Unit, (iii) the assembly and delivery of two complete First
Initial Emulation Units (including some SGI system), one to be used by SGI and
one to be used by the Company.
SECOND INITIAL EMULATION UNIT.
The parties contemplate that the Second Initial Emulation Unit will consist of a
pre-released LSI chip set with a hardware interface to some SGI machine (e.g.
Indy). The parties contemplate that SGI's tasks for the Second Initial Emulation
Unit will include the following: (i) designing the hardware and implementation
for a small production (20 - 30 units) (iii) developing software for the Second
Initial Emulation Unit, and (iv) the assembly and delivery of twenty (20)
complete Second Initial Emulation Units (including some SGI system), five (5) to
be used by SGI and fifteen (15) to be used by the Company.
SGI DELIVERABLE FOR FIRST INITIAL EMULATION UNIT: SGI shall deliver to the
Company one First Initial Emulation Unit (hardware, software, and technical
documentation). SGI to provide software updates for the First Initial Emulation
Unit via a quick and efficient distribution method. SGI shall make additional
First Initial Emulation Units available to the Company for purchase by the
Company at SGl's cost (First Initial Emulation Units supplied at SGI's cost not
to exceed 20) (additional First Initial Emulation Units not included in the
Budget).
DESIRABLE TARGET DATE FOR SGI DELIVERABLE FOR FIRST INITIAL EMULATION UNIT:
May 31, 1994.
LATEST TARGET DATE FOR SGI DELIVERABLE FOR FIRST INITIAL EMULATION UNIT:
July 31, 1994.
SGI DELIVERABLE FOR SECOND INITIAL EMULATION UNIT: SGI shall deliver to the
Company one Second Initial Emulation Unit (hardware, software, and technical
documentation). SGI to provide software updates for the Second Initial Emulation
Unit via a quick and efficient distribution method. SGI shall make additional
Second Initial Emulation Units available to the Company for purchase by the
Company (additional Second Initial Emulation Units not included in the Budget).
DESIRABLE TARGET DATE FOR SGI DELIVERABLE FOR SECOND INITIAL EMULATION
UNIT: January 1, 1995.
LATEST TARGET DATE FOR SGI DELIVERABLE FOR SECOND INITIAL EMULATION UNIT:
March 31, 1995.
5. LICENSEE EMULATION UNIT.
DESCRIPTION: Company anticipates that Company will design (or have a third party
design) an "Licensee Emulation Unit," which is defined as a home box made by
using the actual LSI chip set from the Consumer Hardware, plus extra control
hardware and interface for programming and debugging purposes. The target dates
for Company's completion of the Licensee Emulation Unit are:
DESIRABLE TARGET DATE FOR COMPLETION OF LICENSEE EMULATION UNIT: March 31, 1995.
LATEST TARGET DATE FOR COMPLETION OF LICENSEE EMULATION UNIT: April 30, 1995.
The cost associated with Company's design of the Licensee Emulation Unit is not
part of the Budget; rather, it is at Company's expense. However, SGI agrees to
provide reasonable consultation and technical advice to Company in connection
with Company's design of the Licensee Emulation Unit.
6. PROGRAMMING ENVIRONMENT(S).
DESCRIPTION: Company shall be responsible for the programming environment(s) for
the Initial Emulation Units and the Licensee Emulation Unit, which
environment(s) may be used by the Company and its video game developers for
programming video games. It is contemplated that the programming environment(s)
for the Initial Emulation Units and Licensee Emulation Units will include a
customized assembler, and a C compiler if applicable, and a computer system such
as Indy, PC and other possible systems. The Company anticipates that Company,
and initial video game developers, will use SGl's Indy for the programming
environment with the Initial Emulation Units.
SGI agrees to consult with and provide technical advice to Company with regard
to the programming environment(s) for the Initial Emulation Units and the
Licensee Emulation Unit.
DESIRABLE TARGET DATE FOR COMPANY'S COMPLETION OF PROGRAMMING ENVIRONMENT
FOR INITIAL EMULATION UNIT: May 31, 1994.
LATEST TARGET DATE FOR COMPANY'S COMPLETION OF PROGRAMMING ENVIRONMENT FOR
INITIAL EMULATION UNIT: July 31, 1994.
DESIRABLE TARGET DATE FOR COMPANY'S COMPLETION OF PROGRAMMING ENVIRONMENT FOR
LICENSEE EMULATION UNIT: March 31, 1995.
LATEST TARGET DATE FOR COMPANY'S COMPLETION OF PROGRAMMING ENVIRONMENT FOR
LICENSEE EMULATION UNIT: April 30, 1995.
7. VISUAL DESIGN ENVIRONMENT.
DESCRIPTION: Company contemplates that it will contract as quickly as possible
with a third party (currently expected to be Alias Research Inc.) to develop
and/or customize the third party's off-the-shelf software to use as the visual
design environment for the Initial Emulation Units and Licensee Emulation Units.
The Company shall make the final decision regarding the choice of the third
party. Because the software for the visual design environment must efficiently
interface with the Initial Emulation Units designed by SGI, SGI and Company
shall jointly be responsible for defining the specification given to the third
party for development and/or modification of the software for the visual design
environment.
DESIRABLE TARGET DATE FOR DELIVERABLE OF VISUAL DESIGN ENVIRONMENT: May 31,
1994.
LATEST TARGET DATE FOR DELIVERABLE OF VISUAL DESIGN ENVIRONMENT: July 31, 1994.
PAYMENT TO THIRD PARTY: If the third party contracted with to do the visual
design environment requires payment of a fee, that expense is not part of the
Budget. Rather, it is at Company's expense.
8. AUDIO DESIGN ENVIRONMENT.
DESCRIPTION: Company contemplates that it will contract as quickly as possible
with a third party (currently not identified) to develop and/or customize the
third party's off-the-shelf software to use as the audio design environment for
the Initial Emulation Units and Licensee Emulation Units. The Company shall make
the final decision regarding the choice of the third party. Because the software
for the audio design environment must efficiently interface with the Initial
Emulation Units designed by SGI, SGI and Company shall jointly be responsible
for defining the specification given to the third party for development and/or
modification of the software for the audio design environment.
DESIRABLE TARGET DATE FOR DELIVERABLE OF AUDIO DESIGN ENVIRONMENT: May 31, 1994.
LATEST TARGET DATE FOR DELIVERABLE OF AUDIO DESIGN ENVIRONMENT: July 31, 1994.
PAYMENT TO THIRD PARTY: If the third party contracted with to do the audio
design environment requires payment of a fee, that expense is not part of the
Budget. Rather, it is at Company's expense.
9. GRAPHICS LIBRARY TUTORIAL AND DEMONSTRATION PACKAGE.
DESCRIPTION: SGI shall be responsible for supplying the Company with one or more
sample game frameworks, source code, algorithms, and commentary illustrating the
use of a library that demonstrates and explains the creation and rendering of
hyper 2D polygons, 3D polygons, and other graphics programming techniques
relevant to the Consumer Hardware. The purpose of this software is to
demonstrate to the Company and its video game developers how hyper 2D and 3D
graphics can be accomplished in video games using the LSI chip set and versions
of the visual design environment, audio design environment, and programming
environment(s). The parties contemplate an introductory package ("Introductory
Package") and then a later more advanced package ("Advanced Package") of the
materials described in this paragraph. By way of example, and not by way of
limitation, the Company and its video game developers will need to understand
how to create a polygon. These packages are intended to assist the Company and
its video game developers in understanding good programming techniques for the
Consumer Hardware. The parties will mutually agree on the release/distribution
of the materials described in this paragraph.
SGI DELIVERABLE: Program source code, supplemented by extensive written
materials described above.
DESIRABLE TARGET DATE FOR SGI DELIVERABLE FOR INTRODUCTORY PACKAGE: May 31,
1994.
LATEST TARGET DATE FOR SGI DELIVERABLE FOR INTRODUCTORY PACKAGE: June 31, 1994.
DESIRABLE TARGET DATE FOR SGI DELIVERABLE FOR ADVANCED PACKAGE: January 31,
1995.
LATEST TARGET DATE FOR SGI DELIVERABLE FOR ADVANCED PACKAGE: March 31, 1995
ATTACHMENT: SCHEDULE A1
Silicon Graphics Confidential Home Box Baseline
SCHEDULE A1
HOME BOX BASELINE
The purpose of this document is to summarize discussions about the baseline
functionality of a future home game box. The baseline functionality is that of
a "hyper" traditional 2D video game. Other functionality such as true 3D
capability is not considered here.
1.DISPLAY
The display is from a full-screen memory image (bit map). The image is double
buffered. (There may be more than one display image, see Display Overlay.)
1.1.DISPLAY FORMAT
The display image size is 320 by 240 for NTSC at 60Hz (50Hz for PAL). A single
fixed pixel clock frequency is desirable, such as 6MHz. Various display formats
are supported:
320x240 non-interlaced. 320x240 non-interlaced with horizontal filtering to
640x240. 320x240 interlaced with vertical filtering to 320-480. 320x240
interlaced with horizontal and vertical filtering to 640x480.
An option may be a 640 by 480 display image. The visible line and pixel start
location and count should be supported. Filtering may be supported through line
buffers in the display hardware.
1.2. DISPLAY OUTPUT
Display output should support analog composite video, S-video, and RGB. The
integration of the video DAC and encoder on chip is desirable. Video output
enhancement filtering such as Clear Vision should be investigated.
1.3. DISPLAY COLOR
The display color is 5/5/5 RGB in a 16 bit pixel. An option may be 8/8/8 RGB.
The display color should be gamma corrected through a lookup table in the
display hardware.
1.3.1. DISPLAY INDEXED COLOR
8 bit indexed color display should be supported. Indexed color display might
use the display gamma correction lookup table or might share the graphics
drawing lookup table.
1.4. DISPLAY OVERLAY
Display overlay of multiple images may be required if sprite performance is less
than optimal. There can be up to four overlay images. The HV starting position
and size of each image can vary. Wraparound of images during display is
supported. Images can be less than full screen size. The images are combined
in a fixed priority order. The combination is by pixel selection between
images, and there is no blending between images during overlay display. A line
buffer may be maintained to combine overlay images and perform line averaging.
2. UPDATE RATE
The maximum image update rate is 60Hz. Slower rates are under software control
by enabling an image buffer switch on vertical retrace. Applications which do
not complete an image in the update time can choose to skip the buffer switch,
or display the incomplete image. Read access to the current display line number
should be supported. A high-resolution counter for timing and profiling is
desirable.
3.SPRITES
3.1. SPRITE PERFORMANCE
The minimum goal is 2000 sprites per update or 120K per second. The average
sprite area is 16 by 16 pixels, or roughly 500K pixels per update, or 30M pixels
per second. More sprites are desirable, such as 2500 or 3000 per update.
Performance to draw the display image 8 or more times per update, or 640K
pixels, is desirable. Sprites can be of any programmable area, within a
performance limit of some maximum total number of sprites per update and total
number of pixels per update. Sprite image data should be aligned on a pixel
boundary (8 or 16 bit), so that no memory padding is needed.
3.2. SPRITE TRANSFORMATIONS
Sprites can be arbitrarily scaled, rotated, translated, and skewed. Perspective
projection should be an option, but may be lower performance. Sprite
transformation precision is 16 bit fixed point. Higher precision, such as
floating point, could be an option at lower performance.
3.3. SPRITE CLIPPING
Sprite geometry should be clipped to display image size. A programmable
clipping rectangle within the display image should also be supported.
3.4. SPRITE DATA
Sprites are defined by polygons and rectangular images. The polygons may
consist of quadrilaterals, triangles, meshes of quadrilaterals, or triangle
strips. Multiple polygons may be used for a single sprite image. All polygons
must be convex and planar. Both 2D and 3D polygons are supported. Sprites with
more than one image should be investigated, including mipmaps with
microtextures.
3.5. SPRITE SAMPLING
Sprite pixels are point sampled. Interpolated sampling may be an option at lower
performance. The quality of various sampling methods, such as linear, bilinear,
and trilinear sampling should be investigated. The effect of noise and/or dither
on sampling should be investigated. Sprite interpolation should include an
option to filter only the pixel transparency or alpha component, so that edges
can be antialiased without blurring colors. Sprite mipmap images should be
investigated. The sprite rendering method is to interpolate sprite pixel
coordinates along the edges and spans of the transformed polygon enclosing the
sprite, and to access the sprite pixel color at those coordinates at each pixel
inside the polygon.
3.6. SPRITE SAMPLING PERSPECTIVE CORRECTION
Sprite sampling coordinates should be corrected for perspective. Approximate
methods such as piecewise linear approximation or curve approximation may be
used.
3.7. SPRITE COLOR
Sprite color can be 5/5/5/1 RGBA. The extra A bit is used for effects such as
translucency. Sprite color can also be 4/4/4/4 RGBA. Sprit color can also be 8
bit indexed color, which for a 5/5/5/ display image is converted to RGB through
a lookup table during drawing. When the display image is indexed color, only
indexed color sprites can be drawn.
3.8. SPRITE SHADING
Gouraud shading of a polygon enclosing a sprite, and the combination of sprite
pixel color with the interpolated polygon color is supported, for effects such
as lighting and haze.
3.9. SPRITE COMBINE
Sprite colors can be combined in several ways: Blend: sprite image translucency
applied to a single color (indexed color only?). Modulate: sprite image color
multiplied by shaded color. Decal: blend sprite image color and shaded colors by
sprite image translucency.
3.10. SPRITE PRIORITY
Sprites are drawn in back-to-front order (painter's algorithm). A per-pixel
depth comparison for sprite priority should be an option. The depth might be 8
bits per pixel. Each sprite has a single 8 bit depth value, and a depth image
equal in size to the display image is compared and updated.
3.11. SPRITE EFFECTS
A conditional write based on sprite pixel transparency is supported. Alpha
blending per sprite pixel is supported, for effects such as translucency,
shadows, and spotlights. Minimum blending functionality is (Source/2 +
Destination/2) and (Destination - Source), while general blending is a multiply
per R,G, and B component. A global alpha value can be multiplied by the sprite
pixel alpha for fade and dissolve. Indexed color display drawing might use a
palette of some number of hues, each of which has several
intensity levels (such as 6 bits of hue and 2 bits of intensity), in order to
support pixel blending by changing the intensity without changing the hue, for
shadows, spotlights, and translucency.
3.12. SPRITE DECOMPRESSION
Sprites (and background images) can be decompressed. One type of decompression
is when the data is loaded from ROM, and this may be lossy methods such as JPEG.
Another type of decompression is during drawing. Indexed color is a kind of
drawing decompression. Other kinds of decompression to be investigated include
run length decoding or and block truncation decoding.
4.BACKGROUND
With a single display image, there is no significant distinction between sprites
and background images, rather backgrounds are simply larger sized sprites. If
display overlay is supported, up to three background image planes and one
foreground plane are supported. The background planes can be scrolled and
panned per update, with or without wraparound.
0.XXXXX
At least 24 channels of audio are supported. Each channel is 16 bits at up to
44.1KHz. The channels are combined into two stereo output channels. Audio is
decompressed from ADPCM. Echo processing is supported on the output channels. A
random noise function is available. Audio input with an integrated ADC is
desired.
6.OTHER
Bus sizing to allow the direct connection of 8 and 16 bit I/O devices should be
supported. DMA from I/O devices such as ROM should be supported.
[XXXXXX]=CERTAIN INFORMATION ON THIS PAGE HAS BEEN OMITTED PURSUANT TO AN ORDER
GRANTING CONFIDENTIAL TREATMENT ISSUED BY THE SECURITIES AND EXCHANGE
COMMISSION.
SCHEDULE B
DEVELOPMENT FEE ADVANCE TOTAL TO BE PAID
ROYALTY ON
1. XXXXXXXXX XXXXXXXXX XXXXXXXXX Already Paid
2. XXXXXXXXX XXXXXXXXX XXXXXXXXX February 8, 1994
3. XXXXXXXXX XXXXXXXXX XXXXXXXXX May 1, 1994
4. XXXXXXXXX XXXXXXXXX XXXXXXXXX August 1, 1994
5. XXXXXXXXX XXXXXXXXX XXXXXXXXX November 1, 1994
6. XXXXXXXXX XXXXXXXXX XXXXXXXXX February 1, 1995
7. XXXXXXXXX XXXXXXXXX XXXXXXXXX May 1, 1995
--------- --------- --------- -----------
TOTAL:XXXXXXXXX XXXXXXXXX XXXXXXXXX
*NCL will make XXXXXXXXX withholding on the advance royalty, so only XXXXXXXXX
will be received by SGI.
