System Architecture. It is recommended that there be a single PCB-Design containing all interfaces for connectors, LCD, switches and buttons.
System Architecture. The VVDC system comprises a WinTV-USB device (details for this device are available at xxxx://xxx.xxxxxxxxx.xxx/html/usb_data.htm) and a personal computer. It is designed for both online and offline operations on a regular personal computer running Windows 2000 or Windows XP. The personal computer used for VVDC system development was a Dell Latitude D600 laptop computer with a Pentium M 1.6 GHz Central Computing Unit, 1-GB memory, and a 32-MB ATI Radeon 9000 video card. It ran the Windows XP Professional operating system. The WinTV-USB device is used for digitizing live video signals. When the VVDC system is executed offline, it reads digitized video images from a storage media, and the WinTV-USB device is not necessary. For online operations, the VVDC system reads real-time images from the WinTV-USB device from the location where a live video signal source is connected. The live video source can be a video cassette player or a video camera. The components of the VVDC system and possible video data sources are shown in Figure 6-1. VVDC Video Data link WinTV USB Card Computer Video Data Source Figure 6-1: Components of the VVDC System The software component of the VVDC system was written in the Microsoft Visual C# programming language. It has six modules: a live video capture module, a user input module, a background extraction module, a vehicle detection module, a shadow removal module, and a length-based classification module. The relationships among these modules are illustrated in Figure 6-2. Details of each module are described in the following sections. Background Extraction Queue Image media Background Extraction Module Nth Image … 2nd Image Live video No Live Video Capture Module Detection line occupied? Yes No Vehicle registered? No Yes Yes User Input Module Vehicle Detection Module Shadow Removal Module Length-Based Classification Module Count long vehicle Count the vehicle USB Port Extracted background Pixel-based length New Frame Get Bounding Box Shadow sample LV threshold Virtual detector Vide capture Edge Detection Compute Centroid Shadow Removal Find the median of color values for each pixel 1st Image Shadow Removal Compute Centroid Edge Detection Get Bounding Box Shadow Removal Module USB Port Live video Vide capture Live Video Capture Module No Detection line occupied? Yes No Vehicle registered? Yes Count the vehicle Vehicle Detection Module
System Architecture. We start with a description on the architecture, security features and thread model.
System Architecture. The PRISMA satellite, placed in a sun synchronous orbit, will focus primarily on the European area of interest, enabling the download of the data on two ground stations located in Italy. Once the panchromatic/hyperspectral images are downloaded on ground, they are archived and processed up to level 2. PRISMA System is articulated in the following integrated segments: − A Space Segment, consisting in a single satellite placed in suitable XXX SSO orbit with an operational lifetime of at least 3+2 years. The satellite (see fig. 1) is made up of: - a Platform, based on the Italian small satellites standard platform already used on MITA and AGILE missions - a Payload, consisting in a Hyperspectral instrument and PAN camera - a Payload Data Handling & Transmission (PDHT) recurrent from COSMO-SkyMed Fig. 1 – PRISMA satellite mock-up • A Ground Segment, comprising various centres located in Italy (see Fig. 2) and including: - A Mission Control Centre (MCC), in charge of mission planning and management - A Satellite Control Centre (SCC), in charge of satellite command and control - An Instrument Data Handling System (IDHS), in charge P/L data reception, archiving, processing and interface with users A dedicated launcher will be used to directly inject the Satellite in its final orbit. The baseline is a XXXX launch, as alternative options, other small launchers such as Dnepr, Eurockot, and PSLV are considered in the satellite design.
System Architecture. In the deliverable D3.1 the design procedure has-been described, as well as how it was exploited for several algorithms: Support Vector Machine training, Xxxxxxx - Xxxxxxx correlation estimator, Count Min Sketch and Exponential Histogram extension were designed. In D3.2 the Mutual Information and Transfer Entropy estimators have been designed using the same methodology. The output of the corresponding hardware models is equivalent to the reference software and so the hardware modules can be used as ―hardware libraries‖: for the Maxeler Platform. As was described in D3.1 the Maxeler Platform architecture is a general purpose, Linux-based server with a powerful FPGA-based coprocessor. Algorithms begin their execution on the processor and the hardware libraries, i.e. the part of the algorithm that has been mapped to hardware are called as a procedure. When the hardware library produces the results it sends them back to the processor and algorithm execution continues from the point on. The user has no knowledge on algorithm execution as software remains the same, the only difference for the user should be the time for the algorithm execution. The system that is formed this way can be connected as a module to the QualiMaster pipeline. XX Xxxxxxx-Xxxxxxx Topology HW Mutual Information Topology Data Transmit Bolt Data Receive Spout Data Transmit Bolt Data Receive Spout Maxeler Server TCP Server Xxxxxxx-Xxxxxxx Mutual Information Module Module PIPELINE INFRASTRUCTURE
System Architecture. The proposed architecture is a software-hardware co-design system, as presented in Figure 6. The software part receives the streaming input data, it updates the data structures with the new data and it streams out the results, while the hardware part implements all the computations. The software code uses multiple threads. As shown in Figure 1, the Storm Topology for the Xxxxxxx- Xxxxxxx algorithm consists of two main components, i.e. the data transmit Bolt and the data receive Spout. These components run independently and concurrently, thus we used multiple concurrently running threads for receiving the streaming data, updating the internal data structures and transmitting streaming results back. The main difference between the new proposed architecture and the previous one, which was proposed in Deliverable D3.1, is the new architecture for the hardware-based implementation of the Xxxxxxx-Xxxxxxx Correlation Estimator that is presented in the next section. Maxeler MPC-C Server FPGA Updated HY Coefficients Previous HY Coefficients Read HY Coefficients Transaction Intervals Stock Transactions Ethernet Shared Memory CPU HY Coefficient Estimator Figure 6: Top level Implementation for HW-based Xxxxxxx-Xxxxxxx Correlation Estimator
System Architecture. The common security requirements of confidentiality, integrity, availability, and non- repudiation, the ReS IoT gives rise to additional security issues regarding the computation of security functions (SFs) on SAs for IoT devices [14]. The Security Layer is the layer providing functions such as authentication encryption, access control, and privacy protection. Furthermore it authenticates stationary and driving vehicles and encrypts personal identification and sensitive information [15]. The fog node receive computation requests and sensed data from various IoT devices and can be implemented in different devices such as edge servers, smart routers, base stations and gateway devices [16]. In addition, it enhance road security by sensing, collecting, and forwarding traffic data from and to vehicles and RSUs to perform suitable action in unwanted traffic circumstances like accidents or blocking [17].
System Architecture. The IVRS architecture consists of an industry standard client/server and computer telephony components. The database server is Sybase System 11, running in a UNIX environment. The voice server component is designed with Dialogic voice cards, the leading computer telephony boards, and Artisoft's Visual Voice, an industry-leading computer telephony software development kit. The IVRS voice servers run on Windows NT, the operating system standard for computer telephony applications. The system architecture has been designed with redundancy to handle component or complete system failure in the event of a disaster; voice servers have dual power supplies, disk-mirroring, and redundant disk arrays. Each voice server acts as a backup to the other in the event of voice server failure. The Sybase database server also has error correcting memory, disk-mirroring, redundant disk arrays, and a backup processing unit. The backup processing unit is linked to the primary unit via Hewlett Packard's Servicegard software. If the primary processing unit fails, the backup processor will replace its functionality within minutes. Backup and Disaster Recovery A disaster recovery plan has been developed and tested to support the IVRS architecture. Its purpose is to minimize interruptions to the IVRS in the event of hardware failures and natural disasters. An alternate site is maintained in Covance's Nashville, Tennessee office to recover IVRSs operations during these types of events. Switching operations to the alternate site is estimated to take less than one hour. This involves Covance's long distance telephone carrier to redirect the toll-free service to the alternate site, as well as Covance staff to activate the backup database server and voice server in Nashville. In the event that Covance temporarily recovers to its alternate site, Covance will transfer data to ACS by diskette or other designated media until operations resume at the Covance Princeton site. Complete backups of all systems and data are performed on a daily basis (seven days/week) and are maintained off-site. System Validation The IVRS software produced and administered by Covance is validated by standards that meet the FDA requirements based on "Guidelines on General Advanced Corneal Systems 20 October 1998 Vitrase(TM) 30 53 Principles of Process Validation" and the Device Manufacturing Practices Parts 211.68 and 820.61. All Covance IVRSs are validated following the Covance Computer System Validation SOP. This ...
System Architecture. Create and maintain a domain for execution to protect the Trusted Computing Base (TCB) from external interference or tampering, so that the TCB may protect its resources via access controls and audit trails.
System Architecture. The control system for the Mikron G05 is based around an Xxxxx-Xxxxxxx Control Logix PLC processor and an Xxxxx-Xxxxxxx Panel View Plus touch screen. [*]
