Gate lag measurements Sample Clauses

Gate lag measurements. Figure 3.4 shows the results from gate lag measurements carried out at different temperatures on the short gate HEMTs. VGS is switched from -14V to -4V at a VDS of 1.5V and the drain-current versus time waveform is measured at temperatures from 30°C to 70°C with a step of 10°C [56]. The experimental data have been fitted using three exponentials iD(t)=iD0+ ∆ID[1-exp(-t/τΟΝ)] with three different constant times τΟΝ (inset Figure 3.4). The three time constants calculated at different temperatures were plotted in an Arrhenius plot to extract the activation energy of the traps involved (see Figure 3.5). The three calculated values (0.25eV, 0.53eV, 0.6eV) are fairly in agreement with the values extracted by means of deep level transient spectroscopy (0.18eV, 0.56eV, 0.76eV) confirming a correct identification of the principal traps present in the devices.
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