Common use of Monitor Clock (Optional) Clause in Contracts

Monitor Clock (Optional). The CFP8 module may supply either a transmitter monitor clock or a receiver monitor clock for 16 x 25 Gb/s or for 8 x 50 Gb/s XXX-4 applications. The monitor clock is intended to be used as a reference for measurements of the optical input or output. If provided, the clock shall operate at a rate relative to the host electrical lane rate of 1/8 or 1/48 or 1/64 of 26.5625 GBd host lane rates. For host lane rates of 25.78125 Gb/s, MCLK can operate at 1/8, 1/32, 1/40 or 1/160 of the host lane rate as listed in Table 4-4. When provided, the MCLK shall be CML differential AC-coupled and terminated within the CFP8 module as shown in Figure 4-1. Detailed clock characteristics are specified in Table 4-3. The user can select the source of the Monitor clock. MDIO register bits to select the source of MCLK for the CFP8 module are located in the VR region. Please refer to Ref. [4] for details. Table 4-3: Optional Monitor Clock Characteristics Min. Typ. Max. Unit Notes Impedance Zd 80 100 120 Ω Frequency See Table 4-4 Output Differential Voltage VDIFF 400 1200 mV Peak to Peak Differential Clock Duty Cycle 40 60 % Table 4-4: CFP8 Module Clocking Signals Clock Name Status I/O M x 26.5625 Gb/s NRZ or M x 26.5625 GBd XXX-4 Default Host Lane Rate Optional Rate REFCLK Optional I 1/170 (156.25 MHz) MCLK Optional O 1/8 (3.3203 GHz) Or 1/48 (553.385 MHz) or 1/64 (415.039 MHz) Clock Name Status I/O M x 25 Gb/s Default Host Lane Rate Datacom Up to 4 x 100GBASE- SR4/LR4/ER4 Telecom Up to 4 x OTU4 REFCLK Optional I 1/160 (161.1328 MHz) or 1/40 (644.5313 MHz) 1/160 (174.7031 MHz) or 1/40 (698.8123 MHz) 1/8 (3.2266 GHz) 1/8 (3.49406 GHz) or or 1/32 (805.665 MHz) 1/32 (873.515 MHz) MCLK Optional O or or 1/40 (644.5313 MHz) 1/40 (698.8123 MHz) or or 1/160 (161.1328 MHz) 1/160 (174.7031 MHz)

Monitor Clock (Optional). The CFP8 module may supply either a transmitter monitor clock or a receiver monitor clock for 16 x 25 Gb/s or for 8 x 50 Gb/s XXX-4 applications. The monitor clock is intended to be used as a reference for measurements of the optical input or output. If provided, the clock shall operate at a rate relative to the host electrical lane rate of 1/8 or 1/48 or 1/64 of 26.5625 GBd host lane rates. For host lane rates of 25.78125 Gb/s, MCLK can operate at 1/8, 1/32, 1/40 or 1/160 of the host lane rate as listed in Table 4-4. When provided, the MCLK shall be CML differential AC-coupled and terminated within the CFP8 module as shown in Figure 4-1. Detailed clock characteristics are specified in Table 4-3. The user can select the source of the Monitor clock. MDIO register bits to select the source of MCLK for the CFP8 module are located in the VR region. Please refer to Ref. [4] for details. Table 4-3: Optional Monitor Clock Characteristics Min. Typ. Max. Unit Notes Impedance Zd 80 100 120 Ω Frequency See Table 4-4 Output Differential Voltage VDIFF 400 1200 mV Peak to Peak Differential Clock Duty Cycle 40 60 % Table 4-4: CFP8 Module Clocking Signals Clock Name Status I/O M x 26.5625 Gb/s NRZ or M x 26.5625 GBd XXX-4 Default Host Lane Rate Optional Rate REFCLK Optional I 1/170 (156.25 MHz) MCLK Optional O 1/8 (3.3203 GHz) Or 1/48 (553.385 MHz) or 1/64 (415.039 MHz) Clock Name Status I/O M x 25 Gb/s Default Host Lane Rate Datacom Up to 4 x 100GBASE- SR4/LR4/ER4 Telecom Up to 4 x OTU4 REFCLK Optional I 1/160 (161.1328 MHz) or 1/40 (644.5313 MHz) 1/160 (174.7031 MHz) REFCLK Optional I or or 1/40 (644.5313 MHz) 1/40 (698.8123 MHz) 1/8 (3.2266 GHz) 1/8 (3.49406 GHz) or or 1/32 (805.665 MHz) 1/32 (873.515 MHz) MCLK Optional O or or 1/40 (644.5313 MHz) 1/40 (698.8123 MHz) or or 1/160 (161.1328 MHz) 1/160 (174.7031 MHz)