Common use of Monitor Clock (Optional) Clause in Contracts

Monitor Clock (Optional). The CFP8 module may supply either a transmitter monitor clock or a receiver monitor clock for 16 x 25 Gb/s or for 8 x 50 Gb/s XXX-4 applications. The monitor clock is intended to be used as a reference for measurements of the optical input or output. If provided, the clock shall operate at a rate relative to the host electrical lane rate of 1/8 or 1/48 or 1/64 of 26.5625 GBd host lane rates. For host lane rates of 25.78125 Gb/s, MCLK can operate at 1/8, 1/32, 1/40 or 1/160 of the host lane rate as listed in Table 4-4. When provided, the MCLK shall be CML differential AC-coupled and terminated within the CFP8 module as shown in Figure 4-1. Detailed clock characteristics are specified in Table 4-3. The user can select the source of the Monitor clock. MDIO register bits to select the source of MCLK for the CFP8 module are located in the VR region. Please refer to Ref. [4] for details.