OPENCL COMPILATION TESTS Sample Clauses

OPENCL COMPILATION TESTS. To verify a flat build approach would be sufficient for the OPERA project various OpenCL designs were compiled to test that timing was met for the PCIe interface. Nallatech has an example Lattice Boltzmann code that is representative of a real HPC problem and can be easily tailored to utilise the entire device. It is rare that an FPGA use more than 80% of the device as designs greater in size than this have trouble routing, which results in a poor fMax or, worse still, failure to meet timing. Compiling the lattice boltzman code utilising > 80% of the DSP logic met timing with an fMax of 226 MHz. This is a typical clock frequency for an OpenCL Arria 10 design. In conclusion, the flat build process will be adequate for the needs of the OPERA project. Device Feature Lattice Boltzman resource requirements ALUTs 118710 Registers 291,960 Logic utilization 129,102 / 251,680 (51 % ) DSP blocks 1,381 / 1,687 (82 % ) Memory bits 33,990,040 / 43,642,880 (78 % ) RAM blocks 2,131 / 2,131 (100 % ) Table 12 : Flat compilation test resources Figure 20 : Flat build of the Lattice Boltzmann code Figure 20 shows the logic placement of an OpenCL lattice Boltzmann code compiled and built using the SOC board support package. The items in red are the logic elements that form part of the BSP, such as the PCIe memory interface. The Items in blue are logic elements that form the OpenCL kernels of the Lattice Boltzmann code.