Processor Model Example Instance Sample Clauses

Processor Model Example Instance. ‌ Figure 5.12: Processor domain example model Figure 5.12 contains an exemplary model at the processor domain, i.e. the internals of a Tile. The model contains two Cores, one RAM and one ROM Memory, a Bus, and a NetworkInterface (NI). All mentioned elements are connected via the Bus. The Ports (black connectors) attached to the Cores and to the NetworkInterface are MasterPorts since they need to be able to initiate communication via the Bus. These MasterPorts are connected to BusMasterInterfaces, and thus, the model elements mentioned above are able to communicate. In contrast, the Memory elements are connected via BusSlavePorts to the BusSlaveInterfaces of the Bus, as these elements do not initiate any communication (passive elements). The left hand side of the NetworkInterface is a model of the gateway to the OnChipNetwork at containing layer (i.e., to the Node layer). The left-most black connector is the OnChipNetworkPort of the Tile that contains the discussed example model. This Port is connected to the NetworkInterface’s OnChipNetworkExport (left connector of NetworkInterface component) that depicts the interface of the processor domain to the on- chip-network. As a result (and also considering the meta-models of the other levels of the DREAMS architecture discussed in the previous sections) the model describes that there is a possible communication route from the two Cores shown in Figure 5.12 to resources in located in other Tiles (via the OnChipNetwork) or Nodes (via OnChipNetworks and OffChipNetworks) . Likewise, the model contains the relevant information to determine routes to the Cores and the Memorys from Figure 5.12 from remote resources. platform::GenericPlatformUnit +getPlatformConnectorUnits() : EList<IPlatformConnectorType>+getTransceiverUnits() : EList<Transceiver>+getReceiverUnits() : EList<Receiver>+getTransmitterUnits() : EList<Transmitter> platform::TransmissionUnit -capacity : EInt platform::GatewayUnit platform::MemoryUnit org.fortiss.af3.platform IHypervisorDomain +getArchitectureDomainName() : EString IVirtualizationLayerDomain Hypervisor HypervisorDomainConnector HypervisorDomainElement InterPartitionComPort InterPartitionComInterface InterPartitionOnChipNetworkExport Partition OnChipNetworkDriver InterPartitionCom MemoryArea HealthMonitorConfiguration HealthMonitorRequirement MemoryRequirement HealthMonitorConnector MemoryConnector «interface» platform::IPlatformPort «interface» platform::IGenericPlatformSourceConnector «inter...
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