Transfer and output characteristics of simulated devices Simulated drain current curves as a function of front gate voltage (Id-Vfg) at low (Vd = - 50 mV) and high drain bias (Vd = - 1 V) are presented in Fig. 2a (left -axis) for a structure with Fw = 10 nm, Fh = 45 nm, εr = 1.7, Nd = 1019 cm-3, and L = 500 nm. The right axis shows the calculated transconductance 𝑔𝑚 = (𝑑𝐼𝑑⁄𝑉𝑓𝑔) which can be indicative of device sensitivity. This figure illustrates the different JNT conduction regimes: (i) Vfg >> Vth for flatband Vfb, the point at which the current is 𝐼𝑑 = 𝑞𝜇𝑁𝑑(𝐹𝑤𝐹ℎ)𝑉𝑑/𝐿 (q: charge and μ: hole mobility) and the JNT becomes a simple resistor, (ii) Vfg < Vfb accumulation, (iii) Vfg = Vfb flatband, (iv) Vfb <Vfg < Vth partial channel depletion, and (iv) Vfg = Vth threshold. Fig. 3b shows the Id-Vd output characteristics for devices with Fw = 10 nm, Fh = 45 nm, L = 500 nm, Nd = 1018 cm-3 and two different gate dielectrics εr = 1.7 (organic monolayer) and εr = 3.9 (SiO2). We can see the normal operation of a p-type junctionless device transitioning from linear to saturation regimes as the drain voltage increases toward more negative values. As expected, below threshold (Vfg > Vth) the p-doped device is off and the drain current Id drops to very low values. As the gate voltage increases the channel becomes depleted of majority carriers (holes) and shuts off even for increasing negative drain voltages. Above Vth, as the drain voltage is increased (towards higher negative drain voltage values) the height of the potential barrier that impedes carriers’ flow (hole conduction current) through the channel is decreased and the current increases in a linear fashion with increasing Vd until saturation is reached. At saturation, the drain current Id reaches a constant value independent of the drain bias Vd. The gate potential efficiently modulates the channel conductance and shuts-off the JNT device for both dielectrics. Fig. 2 curves are representative of all simulated devices to be presented here. Figure 2a Id-Vfg (left) and gm (right) at low (Vd = - 50 mV) and high (Vd = -1 V) drain potentials for a device with Fw = 10 nm, Fh = 45 nm Nd = 1019 cm-3, εr = 1.7 and L = 500 nm. 3b. Id-Vd output characteristics for Vfg = -2, -1.5, -1, -0.5, and 0 V for a devices with Fw = 10 nm, Fh = 45 nm L = 500 nm for Nd = 1018 cm-3 for different gate dielectrics.
