Exhibit 10.4
CONFIDENTIAL
------------
----------------------------------
SEMICONDUCTOR TECHNOLOGY LICENSE AGREEMENT
BETWEEN
INTEL CORPORATION
AND
RAMBUS INC.
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*** Confidential treatment requested for portions of this exhibit.
TABLE OF CONTENTS
SECTION 1 DEFINITIONS.......................................................1
1.1 Rambus-1 Interface Technology........................................1
1.2 Rambus-D Interface Technology........................................2
1.3 Rambus Interface Technology..........................................2
1.4 Rambus-1 Interface Specification.....................................2
1.5 Rambus-D Interface Specification.....................................2
1.6 Compatible...........................................................2
1.7 Rambus Memory........................................................2
1.8 Rambus DRAM..........................................................3
1.9 Rambus-D DRAM........................................................3
1.10 Rambus Logic Chip...................................................3
1.11 Rambus ICs..........................................................3
1.12 Cache Memory Interface..............................................3
1.13 Rambus Memory Interface.............................................3
1.14 Other Logic Chip....................................................3
1.15 Rambus Module.......................................................4
1.16 Rambus Board........................................................4
1.17 Rambus System.......................................................4
1.18 RD-AC...............................................................4
1.19 [***]
1.20 RD-MC...............................................................4
1.21 [***]
1.22 Rambus Intellectual Property Rights.................................4
1.24 Confidential Information............................................5
1.25 CNDA................................................................5
1.26 Intel Improvements..................................................5
1.27 Applicable Intel Intellectual Property Rights.......................5
1.28 Development.........................................................5
1.29 Joint Development...................................................5
1.30 Sell................................................................6
1.31 Most Favored Customer Price.........................................6
1.32 Net Sales...........................................................6
1.33 Success Determination Date..........................................6
1.34 Subsidiary..........................................................6
1.35 Effective Date......................................................6
1.36 Prior Agreement.....................................................6
SECTION 2 RAMBUS LICENSES TO INTEL..........................................7
2.1 Manufacturing and Distribution Rights................................7
2.2 Sublicense Rights....................................................8
2.3 Proprietary Markings.................................................8
2.4 Trademarks...........................................................8
2.5 Limitations..........................................................9
[*] Confidential treatment requested.
TABLE OF CONTENTS
(continued)
SECTION 3 INTEL LICENSES TO RAMBUS.........................................10
3.1 Applicable Intel Intellectual Rights................................10
SECTION 4 ENGINEERING OBLIGATIONS AND COOPERATION..........................11
4.1 Engineering Obligations.............................................11
4.2 [***]
4.3 Continuing Obligations of Rambus....................................12
4.4 Liaison and Meetings................................................14
4.5 Meetings with DRAM Licensees........................................14
4.6 Future Memory Interface Cooperation.................................14
4.7 Rambus Warranty Disclaimer..........................................14
4.8 Intel Warranty Disclaimer...........................................15
SECTION 5 ENGINEERING FEE, ROYALTIES, AND WARRANT..........................15
5.1 Engineering Fee.....................................................15
5.2 Royalties to Rambus.................................................16
5.3 Payments and Accounting.............................................17
5.4 Royalties to Intel..................................................18
5.5 Warrant and Board Rights............................................20
5.6 Certain Transactions................................................20
SECTION 6 CONFIDENTIAL INFORMATION.........................................21
6.1 Confidential Information............................................21
6.2 Confidentiality.....................................................22
6.3 Disclosures to DRAM Companies.......................................22
6.4 Exceptions..........................................................23
6.5 CNDA................................................................24
6.6 Residuals...........................................................24
SECTION 7 INTELLECTUAL PROPERTY OWNERSHIP..................................24
7.1 Ownership...........................................................24
7.2 Rambus Indemnification Disclaimer...................................25
7.3 Intel Indemnification Disclaimer....................................25
SECTION 8 LIMITATION OF LIABILITY..........................................25
SECTION 9 TERM AND TERMINATION.............................................26
9.1 Term................................................................26
9.2 Termination.........................................................26
9.3 Survival............................................................27
SECTION 10 GOVERNING LAW AND ARBITRATION...................................28
10.1 Governing Law......................................................28
10.2 Arbitration........................................................28
10.3 Equitable Relief...................................................28
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[*] Confidential treatment requested.
TABLE OF CONTENTS
(continued)
SECTION 11 MISCELLANEOUS...................................................29
11.1 Confidentiality of Agreement.......................................29
11.2 Assignment.........................................................30
11.3 Authority..........................................................30
11.4 Notices............................................................30
11.5 Intel Technical Contact............................................30
11.6 Export Controls....................................................30
11.7 Counterparts.......................................................30
11.8 Partial Invalidity.................................................30
11.9 Relationship of Parties............................................31
11.10 Modification......................................................31
11.11 Waiver............................................................31
11.12 Force Majeure.....................................................31
11.13 Section Headings..................................................31
11.14 Prior Agreement...................................................31
11.15 Entire Agreement..................................................32
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SEMICONDUCTOR TECHNOLOGY LICENSE AGREEMENT
This Semiconductor Technology License Agreement (the "Agreement") is
entered into as of the Effective Date, by and between Rambus Inc., a California
corporation with principal offices at 0000 Xxxxxx Xxxxxx, Xxxxxxxx Xxxx,
Xxxxxxxxxx 00000 ("Rambus") and Intel Corporation, a Delaware corporation having
a place of business at 0000 Xxxxxxx Xxxxxxx Xxxxxxxxx, Xxxxx Xxxxx, Xxxxxxxxxx
00000 ("Intel"). Rambus and Intel may hereafter be referred to individually as a
"Party" or collectively as the "Parties".
WHEREAS, Rambus has developed and is developing certain semiconductor
technology, including a dynamic random access memory interface,
microprocessor/peripheral interface, system bus technology, system bus protocol,
protocol digital logic and high speed signaling/clock circuitry;
WHEREAS, Rambus desires to license to Intel, and Intel desires to
license from Rambus, such technology for use in the manufacture of integrated
circuits proprietary to Intel;
WHEREAS, in connection with this license, the Parties desire that Intel
participates with Rambus in the development of a Rambus-D Interface
Specification (as such term is defined hereinbelow); and
WHEREAS, the Parties desire to terminate and supersede the Prior
Agreement (as such term is defined hereinbelow) pertaining to Rambus-1 Interface
Technology (as such term is defined hereinbelow);
NOW, THEREFORE, IN CONSIDERATION OF THE FOREGOING AND THE MUTUAL
COVENANTS CONTAINED HEREIN, THE PARTIES AGREE AS FOLLOWS:
SECTION 1
1. DEFINITIONS
For purposes of this Agreement the following terms shall have the
meanings set forth below:
1.1 Rambus-1 Interface Technology. "Rambus-1 Interface Technology"
means the following items which are owned by Rambus (or
licensed to Rambus with the right to grant sublicenses of the
scope granted herein without payment of consideration to third
parties):
(a) the bus interface technology described in Exhibit A
hereto, including the features and functions shown
within the dotted line blocked-in area of the diagram
in Exhibit A, but excluding all features and
functions outside such area; and
(b) all information, inventions, technology, technical
documentation, designs (including circuit designs),
materials and know-how which describe use
of such bus interface technology and which Rambus
provides or provided Intel during the course of
implementing this Agreement or the Prior Agreement.
1.2 Rambus-D Interface Technology. "Rambus-D Interface Technology"
means the following items which are owned by Rambus (or
licensed to Rambus with the right to grant sublicenses of the
scope granted herein without payment of consideration to third
parties):
(a) the bus interface technology described in Exhibit B
hereto, including the features and functions shown
within the dotted line blocked-in area of the diagram
in Exhibit B, but excluding all features and
functions outside such area; and
(b) all information, inventions, technology, technical
documentation, designs (including circuit designs),
materials and know-how which describe use of such bus
interface technology and which Rambus provides Intel
during the course of implementing this Agreement.
1.3 Rambus Interface Technology. "Rambus Interface Technology"
means Rambus-1 Interface Technology and Rambus-D Interface
Technology.
1.4 Rambus-1 Interface Specification. "Rambus-1 Interface
Specification" means, at any time, the then most current
version of the interface specification for the Rambus-1
Interface Technology, as such interface specification is
finalized and released by Rambus.
1.5 Rambus-D Interface Specification. "Rambus-D Interface
Specification" means, at any time, the then most current
version of the interface specification for the Rambus-D
Interface Technology, as such interface specification is
issued and released by Rambus.
1.6 Compatible. "Compatible" (including "Compatibility" and other
variants), as applied to an integrated circuit, means that the
integrated circuit is fully compatible with either the
Rambus-1 Interface Specification or the Rambus-D Interface
Specification such that the integrated circuit can communicate
with other integrated circuits manufactured by licensees of
Rambus which comply with the Rambus-1 Interface Specification
or the Rambus-D Interface Specification, as applicable, and
shall include protocol, pin function, pin sequencing, pin
pitch and electrical specifications compatibility.
1.7 Rambus Memory. "Rambus Memory" means each integrated circuit
with a principal function of memory storage which (i)
incorporates all or part of the Rambus Interface Technology,
(ii) is defined and designed by or for Intel, (iii) is
Compatible, and (iv) except as set forth in Section 2.4 below,
bears only Intel's trademark and part number (except in the
case of samples, prototypes and other low volume
non-commercial products). An integrated circuit which contains
memory cells integrated with a RD-MC and RD-AC for controlling
Rambus-D DRAMs is not considered a Rambus Memory as long as it
has major
functions other than memory storage, logic gate count exceeds
forty thousand (40,000) gates, and its memory cells are not
accessed via a RD-AC.
1.8 Rambus DRAM. "Rambus DRAM" means each Compatible integrated
circuit which is a dynamic random access memory (DRAM).
1.9 Rambus-D DRAM. "Rambus-D DRAM" means each Rambus DRAM which is
Compatible with the Rambus-D Interface Specification.
1.10 Rambus Logic Chip. "Rambus Logic Chip" means each integrated
circuit, other than a Rambus Memory, which (i) incorporates
all or part of the Rambus Interface Technology, (ii) is
defined and designed by or for Intel, (iii) is Compatible, and
(iv) except as set forth in Section 2.4 below, bears only
Intel's trademark and part number (except in the case of
samples, prototypes and other low volume non-commercial
products).
1.11 Rambus ICs. "Rambus ICs" means Rambus Memories and Rambus
Logic Chips.
1.12 Cache Memory Interface. "Cache Memory Interface" means the
memory interface that:
(a) the sole function of which is to connect directly to
local cache memory;
(b) is in addition to a clearly distinct separate main
memory interface; and
(c) connects, directly or indirectly, to less than ten
percent (10%) of the total number of bits of
semiconductor memory connected, directly or
indirectly, to the processor, with at least ninety
percent (90%) of the total number of bits of
semiconductor memory connected via the main memory
interface.
1.13 Rambus Memory Interface. "Rambus Memory Interface" means any
memory interface the manufacture, sale or use of which would,
unless licensed by Rambus, infringe any Rambus Intellectual
Property Right.
1.14 Other Logic Chip. "Other Logic Chip" means each integrated
circuit which (i) does not have a principal function of memory
storage, (ii) is defined and designed by or for Intel, (iii)
is not Compatible, (iv) does not include any Rambus Memory
Interface other than a Cache Memory Interface, and (v) bears
only Intel's trademark and part number (except in the case of
samples, prototypes and other low volume non-commercial
products). "Other Logic Chip" includes, without limitation,
integrated circuits complying with the foregoing that
integrate cache control logic and SRAM cache memory.
1.15 Rambus Module. "Rambus Module" means each product
incorporating any Rambus ICs on a substrate (such as silicon,
ceramic or a PC board) with multiple integrated circuits
attached which are not in their own packages.
1.16 Rambus Board. "Rambus Board" means each product, other than
Rambus Modules, incorporating any Rambus ICs or Rambus Modules
in a card or other board product which adds material value to
the Rambus ICs or Rambus Modules.
1.17 Rambus System. "Rambus System" means each product
incorporating any Rambus ICs, Rambus Modules and/or Rambus
Boards in a system which adds material value to the Rambus ICs
or Rambus Modules.
1.18 RD-AC". "RD-AC" means the cell incorporating Rambus-D
Interface Technology on a Rambus Logic Chip which a controller
uses to convert the Rambus-D Interface Technology signals on
the Rambus-D Interface Technology channel to a lower
frequency, wider CMOS level internal bus to which the
controller CMOS logic can directly connect.
1.19 [***]
1.20 RD-MC". "RD-MC" means the memory controller logic on a Rambus
Logic Chip which converts from the RD-AC internal interface to
a more conventional interface.
1.21 [***]
1.22 Rambus Intellectual Property Rights. "Rambus Intellectual
Property Rights" means all patents, patent applications,
copyrights, trade secrets and other similar intellectual
property rights as known by other names in all countries of
the world which, during the term of this Agreement, are owned
by Rambus or licensed to Rambus with respect to which Rambus
has the right to grant sublicenses of the scope granted herein
without payment of consideration to third parties and which
are necessary to implement the Rambus Interface Technology,
including all patents , patent applications, copyrights, trade
secrets and other similar intellectual property rights as
known by other names in all countries of the world owned by
Rambus which are necessary to implement the [***] or
improvements thereto which Rambus has made generally available
to its Rambus-D Interface Technology licensees. Nothing in
this section shall obligate Rambus to develop or deliver to
Intel any technical information.
1.23 Additional Rambus Rights. "Additional Rambus Rights" means all
patents, patent applications, copyrights, trade secrets and
other similar intellectual property rights in all countries of
the world, other than Rambus Intellectual Property Rights,
which, during the term of this Agreement, are owned by Rambus
or licensed to Rambus with the right to grant sublicenses of
the scope granted herein without payment of royalties.
1.24 Confidential Information. "Confidential Information" has the
meaning set forth in Section 6.1 below.
[*] Confidential treatment requested.
1.25 CNDA. "CNDA" means the Parties' March 12, 1993 "Corporate
Non-Disclosure Agreement" (CNDA #10742), and includes all
Confidential Information Transmittal Records (CITRs) pursuant
thereto.
1.26 Intel Improvements. "Intel Improvements" means all upgrades,
enhancements, improvements or other derivatives of Rambus
Interface Technology which are or have been made, acquired or
licensed by Intel or Intel Subsidiaries.
1.27 Applicable Intel Intellectual Property Rights. "Applicable
Intel Intellectual Property Rights" means all patents, patent
applications, copyrights, trade secrets, and other similar
intellectual property rights as known by other names (except
mask work rights and trademark rights) in all countries of the
world to the extent necessary to implement any Rambus
Interface Technology or Intel Improvements, in a memory
interface, and which, during the term of this Agreement, are
owned by Intel or Intel Subsidiaries (or licensed to Intel or
Intel Subsidiaries with respect to which Intel has the right
to grant sublicenses of the scope granted herein without
payment of consideration to third parties). "Applicable Intel
Intellectual Property Rights" does not include Intel
intellectual property rights relating to (i) architecture or
applications which are made possible by using the Rambus
Interface Technology but which do not constitute bus
architecture technology, or (ii) semiconductor manufacturing
technology, or (iii) any Intel Improvement to the [***];
unless necessary to ensure functionality of the
Rambus-D Interface Technology. "Necessary to ensure
functionality" means changes in the [***] which
necessitate changes in the Rambus-D DRAM. Nothing in this
section shall obligate Intel to develop or deliver to Rambus
any technical information.
1.28 Development. "Development" means any idea,
invention (whether or not patentable), copyrightable work, or
other technology conceived or developed in connection with the
development pursuant to Section 4 of this Agreement, or prior
activities relating to such development commencing November
29, 1995.
1.29 Joint Development. "Joint Development" means each Development
made jointly by the Parties. Whether a Development is joint
shall be determined with respect to the United States patent
law (whether or not the development is patentable) or, with
respect to original works of authorship, with respect to
United States copyright law.
1.30 Sell. To "Sell" a product or item means to sell, lease, or
otherwise transfer or dispose of the product or item, or to
commence internal productive use thereof. ("Sold," "Sale," and
other forms of "Sell" shall have the same meaning.)
1.31 Most Favored CustomerPrice". "Most Favored Customer Price"
means the lowest price offered by Rambus to its customers or
potential customers for the same or functionally similar goods
irrespective of volume or geography.
1.32 Net Sales. "Net Sales" of a company with respect to a product
means the gross sales amount invoiced or otherwise charged to
customers of that company or its Subsidiaries for all such
products, less amounts invoiced for returned goods for which a
refund is given, less separately stated charges for insurance,
handling,
[*] Confidential treatment requested.
duty, freight and taxes where such items are included in the
invoiced price. In the case of products transferred by that
company to a Subsidiary for resale by such Subsidiary, only
the final Sale by the Subsidiary shall be included in the
Net Sales amount.
1.33 Success Determination Datebsidiary. "Success Determination
Date" means the date on which all of the following are
satisfied: (i) twelve (12) months after the sale in the normal
course of business, in aggregate by all manufacturers thereof,
of one million (1,000,000) Rambus-D DRAMs, (ii) twelve (12)
months after [***] (iii) a total of six (6) suppliers are able
to ship one million (1,000,000) units per month Rambus-D
DRAMs, and (iv) for at least three (3) of such six (6)
suppliers, the cost of Rambus-D DRAM is within five percent
(5%) of the cost of 100MHz 4Mbitx16 SDRAM manufactured on the
identical process.
1.34 Subsidiary. "Subsidiary" of a company means a corporation or
other entity of which more than fifty percent (50%) of the
stock or other equity interests entitled to vote for the
election of directors or equivalent governing body is owned by
that company , but such corporation or other entity shall be
deemed to be a Subsidiary only so long as such ownership
exists.
1.35 Effective Date. "Effective Date" means the date of signing by
the second Party to sign this Agreement, provided that if by
November 30, 1996 the other Party has not signed this
Agreement, the first Party's signature shall become void
unless otherwise agreed in writing.
1.36 Prior Agreement. "Prior Agreement" means the Parties'
Intel/Rambus Semiconductor Technology License Agreement,
effective March 22, 1993.
SECTION 2
2. RAMBUS LICENSES TO INTEL
2.1 Manufacturing and Distribution Rights2.1 Manufacturing and
Distribution Rights.
(a) Commencing on the Effective Date and subject to the terms
and conditions of this Agreement, Rambus hereby grants to
Intel a worldwide, nonexclusive, nontransferable license:
(i) under the Rambus Intellectual Property Rights to
design, make, have made (subject to Section 2.1(b)
below), use, import, offer to Sell, and Sell
Rambus ICs, alone or incorporated into Rambus
Modules, Rambus Boards, and Rambus Systems,
provided that, with respect to any intellectual
property rights of Rambus licensees which are
licensed to Rambus in connection with the
licensee's Rambus interface technology license
agreement with
[*] Confidential treatment requested.
Rambus, Intel's license pursuant to this paragraph
(i) shall be limited to implementation of the
Rambus Interface Technology, and no license with
respect thereto is granted for use in any other
portion of any Rambus IC; and
(ii) under the Rambus Intellectual Property Rights and
the Additional Rambus Rights to design, make, have
made (subject to Section 2.1(b) below), use,
import, offer to Sell, and Sell Other Logic Chips,
alone or incorporated into modules, boards, and
systems, provided, however, that no license is
granted pursuant to this Section 2.1(a)(ii) with
respect to any intellectual property rights of
Rambus licensees which are licensed to Rambus in
connection with the licensee's Rambus interface
technology license agreement with Rambus, and no
license is granted with respect to any Rambus
Memory Interface other than Cache Memory
Interfaces.
(b) Intel shall have the right to subcontract manufacturing of
all or part of Rambus ICs and Other Logic Chips provided
that (i) subcontractors only receive mask sets or data
bases, and (ii) each subcontractor agrees in writing not to
use Rambus Interface Technology for any purpose other than
such subcontract manufacturing for Intel. Nothing herein
shall be deemed to grant Intel subcontractors any license
under the Rambus Interface Technology except for performing
subcontract manufacturing for Intel as provided herein.
(c) Rambus agrees not to seek royalties or other consideration
from any purchaser of Intel CPUs, with respect to use of any
Rambus Intellectual Property Rights by such Intel CPU
purchasers in packaging, connecting, clock sourcing, or
otherwise implementing, in a Rambus Board or Rambus System,
the combination of Intel CPUs and both Rambus ICs and Rambus
DRAMs manufactured and sold under license from Rambus. In
addition, Rambus agrees not to seek royalties or other
consideration for the use of any Rambus Intellectual
Property Rights by suppliers to the such purchaser of Intel
CPUs, for their manufacture and sales of packages,
connectors, PC boards, termination schemes, and clock
sources to such purchaser of Intel CPUs.
2.2 Sublicense Rights. Intel shall have the right to grant
-----------------
sublicenses of the rights granted in Section 2.1 above only to
Subsidiaries of Intel; provided, that (i) Intel shall cause each
Subsidiary to agree to be bound by the terms and conditions of
this Agreement, excluding the provisions of this paragraph and
the provisions for fees contained in Section 5.1 below, and (ii)
such sublicense will co-terminate upon termination of the
corresponding rights granted in Section 2.1, above. The services
specified in Section 4 are the services to be provided by Rambus,
in the aggregate, for Intel and its sublicensed Subsidiaries.
Intel shall itself pay royalties accrued by sublicensed
Subsidiaries. Rambus' audit rights pursuant to Section 5.3 below
shall apply to all sublicensed Subsidiaries. Intel shall be
responsible for the performance by each Subsidiary of all
obligations contained herein.
-7-
2.3 Proprietary Markings. To the extent that Intel generally marks
--------------------
its own packaging or documentation with its own patent numbers
covering the goods it manufactures, Intel shall likewise xxxx the
packaging or documentation of the Rambus ICs or Rambus Modules
manufactured by or for Intel with the Rambus patent numbers which
apply to such Rambus ICs and Rambus Modules. The Parties
acknowledge that Intel does not so xxxx its own packaging or
documentation as of the Effective Date of this Agreement.
2.4 Trademarks.
----------
(a) Rambus hereby grants to Intel a nonexclusive, royalty free,
paid-up, worldwide license under the Rambus trademarks
specified in Exhibit C, as amended by Rambus from time to
time ("Trademarks") to use, xxxx and Sell Rambus ICs in
accordance with this section. No rights are granted pursuant
to this section except with respect to Rambus Trademarks.
(b) To the extent that Intel uses the Trademarks in Intel
catalogues, brochures and other marketing material used for
Rambus ICs and Rambus Modules, Intel will appropriately
designate the Trademarks and their origin. All
representations of Rambus' Trademarks that Intel uses shall
first be reviewed with Rambus for design, color and other
details or shall be exact duplicates of those used by
Rambus.
(c) Intel [***] visibly xxxx each Rambus IC with the Trademarks.
(d) If marked by Intel: (i) Intel shall use the Trademarks in
accordance with the instructions from Rambus and agrees that
Rambus may from time to time revise these instructions for
the purpose of protecting the standards of performance
established for Rambus' goods and services sold under the
Trademarks, (ii) at Rambus' request from time to time, Intel
will provide to Rambus, at no charge, samples of Intel's
Rambus ICs to enable Rambus to ensure that such Rambus ICs
are of appropriate quality, and (iii) Intel will work with
Rambus to remedy any failure of its Rambus ICs to meet the
reasonable quality standards established by Rambus for goods
bearing the Trademarks.
2.5 Limitations. No license or other right is granted, by
-----------
implication, estoppel or otherwise, to Intel under any patents,
confidential information or other intellectual property rights
now or hereafter owned or controlled by Rambus except for the
licenses and rights expressly granted in this Agreement. In
addition, Intel shall have no right to manufacture or distribute
or authorize its customers to use or distribute integrated
circuits which incorporate all or part of Rambus Interface
Technology other than Rambus ICs and Other Logic Chips, even if
such integrated circuits are incorporated in Rambus Modules or
other modules, Rambus Boards or other boards, or Rambus Systems
or other systems. Nothing contained in this Agreement shall be
construed as:
-8-
[*] Confidential treatment requested.
(a) warranty or representation by Rambus as to the validity,
enforceability, and/or scope of any Rambus Intellectual
Property Right, except that Rambus hereby represents and
warrants that as of the Effective Date hereof, to the best
of Rambus' information and belief, there are no actual or
alleged claims against any of such Rights;
(b) imposing upon Rambus any obligation to institute any suit or
action for infringement of any Rambus Intellectual Property
Right, or to defend any suit or action brought by a third
party which challenges or concerns the validity,
enforceability, or scope of any Rambus Intellectual Property
Right, provided however, that Rambus shall cooperate with
Intel in the defense any such action brought against Intel;
(c) imposing on Rambus any obligation to file any patent
application or other intellectual property right application
or registration or to secure or maintain in force any patent
or other Rambus Intellectual Property Right; or
(d) a warranty or representation by Rambus as to the
performance, operation or maintenance of any product of
Intel manufactured, used or sold pursuant to this Agreement.
SECTION 3
3. INTEL LICENSES TO RAMBUS
3.1 Applicable Intel Intellectual Property Rights
---------------------------------------------
(a) Intel hereby grants Rambus a worldwide, royalty free and
fully paid (except for the royalty sharing set forth in
Section 5.4 below), nonexclusive license under Applicable
Intel Intellectual Property Rights to design, make, have
made, use, import, offer to Sell, and Sell any products
which incorporate all or part of Rambus Interface Technology
or any other Rambus interface technology, provided that
Rambus' rights with respect to the Applicable Intel
Intellectual Property Rights shall be limited to
implementation of the Rambus interface technology, and no
license with respect thereto is granted for use in any other
portion of any integrated circuit including the core of a
memory IC (i.e. that portion of a memory IC other than the
interface). Rambus shall have the right to sublicense its
rights under the Applicable Intel Intellectual Property
Rights to any or all of the other licensees of any Rambus
Interface Technology or any other Rambus interface
technology.
(b) No license or other right is granted, by implication,
estoppel or otherwise, to Rambus under any patents,
confidential information or other intellectual property
rights now or hereafter owned or controlled by Intel except
for the licenses and rights expressly granted in this
Agreement. Nothing contained in this Agreement shall be
construed as:
-9-
(i) a warranty or representation by Intel as to the
validity, enforceability, and/or scope of any
Applicable Intel Intellectual Property Right;
(ii) imposing upon Intel any obligation to institute any
suit or action for infringement of any Applicable Intel
Intellectual Property Right, or to defend any suit or
action brought by a third party which challenges or
concerns the validity, enforceability, or scope of any
Applicable Intel Intellectual Property Right;
(iii) imposing on Intel any obligation to file any patent
application or other intellectual property right
application or registration or to secure or maintain in
force any patent or other Applicable Intel Intellectual
Property Right; or
(iv) a warranty or representation by Intel as to the
performance, operation or maintenance of any product of
Rambus or its sublicensees manufactured, used or sold
pursuant to the license in Section 3.1(a) above.
SECTION 4
4. ENGINEERING OBLIGATIONS AND COOPERATION
4.1 Engineering Obligations.
-----------------------
(a) Rambus will use its reasonable best efforts to define,
design, develop and market the Rambus-D Interface
Specification for implementation in Rambus-D DRAMs and in
Intel's PC main memory control chipsets, working with Intel
and other Rambus-D DRAM licensees, as set forth in Exhibit
D. [***].
(b) Intel will use its reasonable best efforts to design,
develop, mass produce, market, and sell a commercially
attractive PC main memory control chipset which implements
the Rambus-D Interface Specification. Intel represents that,
as of the Effective Date, the activities pursuant to this
Section 4.1 are anticipated to be Intel's main effort to
develop a new interface for PC main memory for mass
production in the period 1999-2002.
(c) Intel and Rambus will each assign a team, appropriately
staffed for accelerated, high priority development, to
accelerate the above-referenced development according to the
timetable and tasks in Exhibit
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[*] Confidential treatment requested.
D. As appropriate and agreed by the Parties, Rambus and
Intel will periodically revise the timetable and tasks in
Exhibit D.
(d) Rambus agrees to develop with Intel up to three (3) RD-ACs
(which three (3) RD-ACs shall include, and not be in
addition to, the RD-AC(s) specified in Exhibit D). The
responsibilities of the Parties with respect to such
development shall be as set forth in Exhibit D or as
otherwise agreed to by the Parties. Intel agrees that at
least one of these RD-ACs will be designed for use in a
commercial Intel product.
(e) Intel will use reasonable efforts to develop for itself
RD-ACs required by Intel in addition to the three (3) RD-ACs
specified in Section 4.1(d) above. If, however,
notwithstanding its reasonable efforts, Intel is unable to
develop a particular RD-AC, Rambus will agree to develop it
for Intel on Rambus' then current Most Favored Customer
Price, terms and conditions for RD-ACs of similar schedule
and complexity.
4.2 [***].
4.3 Continuing Obligations of Rambus
--------------------------------
(a) Rambus will promptly provide Intel updates to the Rambus
Interface Specifications provided to Intel, as required to
enable Intel to maintain Compatibility.
(b) For purposes of this Section, version 0.3 of the Rambus-D
Interface Specification shall mean the initial, preliminary
Rambus-D Interface Specification issued by Rambus, and
version 1.0 of the Rambus-D Interface Specification (or a
subspecification thereof as described below) shall mean the
version which Rambus then intends to be final for
implementation by Rambus-D Interface Technology licensees,
but is still subject to change as necessary to address
unforeseen implementation difficulties and/or tradeoffs. It
is understood that the Rambus-D Interface Specification,
over time, will be comprised of multiple subspecifications
which will not be mutually exclusive and may co-exist at any
time. For example, there may be a [***] that co-exists in
the market with a [***] and/or a subspecification
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[*] Confidential treatment requested.
for a graphics optimized version of a [***] as well as a
subspecification for a PC main memory optimized version of a
[***].
(c) Prior to any material change by Rambus to any version of the
Rambus-D Interface Specification prior to version 1.0,
Rambus will provide to Intel reasonable notice and an
opportunity to confer with Rambus concerning the change.
Intel has designated to Rambus in Section 11.5, an Intel
representative authorized to receive this notice and to act
on Intel's behalf with respect thereto and with respect to
Section 4.3(e) below (the "Intel Technical Contact").
(d) For each version of the Rambus-D Interface Specification up
to version 1.0, except for version 0.3, Rambus agrees to
provide to Intel, for review by Intel, the initial draft
final version thereof at least seven (7) business days prior
to Rambus' release of that version. Rambus agrees to
consider in good faith any written comments or suggested
changes by Intel to that version. It is understood that
modifications to the version provided by Rambus to Intel
pursuant to this section, whether as a result of Intel's
comments or suggested changes, third party comments,
observations by Rambus, or otherwise, will not restart the
seven (7) day period, and that at any time at least seven
(7) business days after providing the draft final version to
Intel, Rambus will be entitled to release that version as
modified by Rambus. However, Rambus will use reasonable best
efforts to notify Intel, and to provide a copy of that
version, to Intel before such release.
(e) Rambus will provide to the Intel-designated Intel Technical
Contact, in writing, notice (the "Notice") of each proposed
modification ("Applicable Modification") to any version 1.0
or later version of any subspecification of the Rambus-D
Interface Specification for a Rambus-D DRAM ("Applicable
Version"). If at the time of any Notice both (i) Intel is
then in volume production on a Compatible main memory
controller based on that Applicable Version, or is using its
reasonable best efforts to develop such a controller, and
(ii) either (A) it is prior to twelve months after the
Success Determination Date, or (B) in any prior two (2)
consecutive calendar quarters at least twenty percent (20%)
of Intel's shipments, by unit volume, of integrated circuits
that control main memory were Compatible, then Rambus will
not implement the Applicable Modification if Intel objects
to the Applicable Modification as follows: Within seven (7)
business days after the Notice, the Intel Technical Contact
shall approve or disapprove the modification in writing.
Intel shall not unreasonably withhold its approval of any
proposed Applicable Modification that is necessary for
achievement of the target specification and schedules of the
applicable Rambus-D DRAM unless Intel can demonstrate that
the Applicable Modification would have substantial negative
consequences to Intel. Failure to respond or disapproval by
Intel of a proposed such modification shall be followed
within fourteen (14) business days by an oral discussion of
all relevant information explaining the basis for Intel's
position, including the negative consequences to Intel of
implementing
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[*] Confidential treatment requested.
the Applicable Modification and a full explanation of the
reasons therefor. Such oral discussion shall be conducted
between respective executives of the Parties and, if not
resolved thereby, Rambus shall have no right to proceed with
including the Applicable Modification. Any such oral
discussion with Intel which does not contain this
information shall be ineffective and shall be deemed an
approval. With respect to any Applicable Modification
disapproved by Intel, Intel shall assist Rambus, and its
Rambus-D DRAM licensees, diligently and in good faith, to
develop alternative modifications that would be acceptable
to Intel and would achieve, to the extent possible, the
goals of the proposed Applicable Modification. Except for
Rambus' Notice obligation, Rambus shall have no obligations,
and Intel shall have no rights, pursuant to this Section
4.3(e) with respect to any Applicable Modification unless
clauses (i) and (ii) hereinabove are satisfied at the time
that Rambus provides the Notice thereof to the Intel
Technical Contact. In addition, Rambus shall have no
obligations, and Intel shall have no rights, pursuant to
this Section 4.3(e) at any time when Intel has not
designated an active Intel Technical Contact in accordance
with this section.
(f) [***]
4.4 Liaison and Meetings. Until completion of the tasks specified in
--------------------
Exhibit D, executives of the Parties will use reasonable best
efforts to meet quarterly, toward the end of each calendar
quarter, to review the status of the development project.
4.5 Meetings with DRAM Licensees. The Parties agree to use reasonable
----------------------------
best efforts to jointly meet quarterly with jointly selected
Rambus Interface Technology DRAM licensees to review progress in
achieving the goals of this Agreement.
4.6 Future Memory Interface Cooperation. If, when Rambus is first
-----------------------------------
ready to license any memory interface technology other than the
Rambus Interface Technology, during both that calendar quarter
and the immediately preceding calendar quarter greater than
twenty percent (20%) of Intel's shipments, by unit volume, of
integrated circuits that control main memory are Compatible, then
Rambus agrees to grant to Intel a license to such memory
interface technology, and to provide engineering support, under
terms and conditions substantially similar to the terms and
conditions of this Agreement. In addition, if Rambus is first
ready to license any memory interface technology other than the
Rambus Interface Technology prior to twelve (12) months after the
Success Determination Date, then Rambus shall grant to Intel a
license, and provide engineering support, under terms and
conditions of agreement substantially similar to the terms and
conditions of this Agreement, provided that the agreement for
such other memory interface technology in which the license and
engineering support are provided shall state that such agreement
shall terminate as of twelve (12)
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[*] Confidential treatment requested.
months after the Success Determination Date, unless during any
two (2) consecutive calendar quarters prior to twelve (12) months
after the Success Determination Date greater than twenty percent
(20%) of Intel's shipments, by unit volume, of integrated
circuits that control main memory are Compatible.
4.7 Rambus Warranty Disclaimer. EXCEPT AS PROVIDED IN SECTION 2.5(a),
--------------------------
THE RAMBUS INTERFACE TECHNOLOGY, TECHNICAL INFORMATION, ITEMS IN
EXHIBIT D, AND CONFIDENTIAL INFORMATION PROVIDED BY RAMBUS TO
INTEL ARE PROVIDED AND LICENSED "AS IS" WITHOUT WARRANTY OF ANY
KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY
IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
PURPOSE.
4.8 Intel Warranty Disclaimer. THE TECHNICAL INFORMATION, ITEMS IN
-------------------------
EXHIBIT D, AND CONFIDENTIAL INFORMATION PROVIDED BY INTEL TO
RAMBUS ARE PROVIDED AND LICENSED "AS IS" WITHOUT WARRANTY OF ANY
KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY
IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
PURPOSE.
SECTION 5
5. ENGINEERING FEE, ROYALTIES, AND WARRANT
5.1 Engineering Fee. Intel shall pay Rambus an engineering fee in the
amount of [***], as follows:
(a) Rambus acknowledges receipt of [***] prior to the
Effective Date.
(b) Upon execution of this Agreement, Intel shall pay
to Rambus [***].
(c) Rambus acknowledges receipt of [***] prior to the
Effective Date in lieu of payment due on September
30, 1996. On or before the last business day of
each calendar quarter thereafter for each of the
[***] succeeding calendar quarters (i.e, until
[***], when a total of [***] has been paid to
Rambus pursuant to this section), Intel shall pay
to Rambus [***], unless Rambus has failed to meet
the Exhibit D milestones for which it was
responsible during that calendar quarter. If,
because of Rambus' failure to complete the
applicable milestone, Intel does not make a
payment pursuant to the preceding sentence on or
before the last business day of the calendar
quarter, Intel shall, within ten (10) business
days thereafter, in writing, either terminate this
Agreement or extend to Rambus an additional sixty
(60) days to cure such failure. If Intel extends
Rambus this additional sixty (60) days, then upon
expiration of this sixty (60) day
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[*] Confidential treatment requested.
period, Intel shall either terminate this Agreement by
written notice to Rambus, or pay to Rambus the [***] payment
for that quarter, regardless of whether Rambus cured the
failure to achieve the milestones for that quarter.
Determination of whether Rambus has met such milestones will
be made in good faith by Intel management, including
evaluation of Intel's own performance, during the quarterly
executive review scheduled toward the end of each quarter.
5.2 Royalties to Rambus.
-------------------
(a) Rambus Logic Chip Royalty.
-------------------------
(i) Commencing [***] and on or before the first
calendar day of each calendar quarter thereafter, Intel
shall pay to Rambus [***]) in consideration of the
license granted to Intel in Section 2.1(a)(i) above
with respect to Rambus Logic Chips. This royalty shall
be [***]. Intel, however, shall be entitled to
terminate this royalty obligation upon written notice
from Intel to Rambus that Intel will immediately cease
manufacturing, or having manufactured, all Rambus Logic
Chips. Upon such notice, Intel's royalty obligation
pursuant to this Section 5.2(a) shall terminate, and
Intel's license, pursuant to Section 2.1(a)(i) above to
design, make, or have made Rambus Logic Chips, shall
permanently and irrevocably terminate, i.e., Intel
shall not be entitled to reinstate this license. Upon
such notice and termination, however, Intel shall
retain the right to Sell (but not to design, make, or
have made) Rambus Logic Chips made by or for Intel
prior to such notice. In addition, unless, as of the
effective date of such notice of termination by Intel,
in each of any two (2) prior consecutive calendar
quarters greater than twenty percent (20%) of Intel's
shipments, by unit volume, of integrated circuits that
control main memory were Compatible, Intel's license,
pursuant to Section 2.1(a)(ii) above, to design, make,
or have made Other Logic Chips shall also permanently
and irrevocably terminate. Upon such termination,
however, Intel shall retain the right to Sell (but not
to design, make, or have made) Other Logic Chips made
by or for Intel prior to such notice.
(ii) If after any [***] Intel shall have the option, on
written notice, [***] after the effective date of such
written notice, and, of the end of such [***] the
license granted in Section 2.1(a)(i) [***]
[*] Confidential treatment requested.
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[***] Should Intel [***] Intel's right to nominate a
representative to the Rambus Board of Directors
pursuant to the Registration Rights Agreement attached
hereto as Exhibit F shall terminate.
(b) Rambus Memory Royalty Rate. In addition to the above, Intel
--------------------------
shall pay to Rambus a royalty equal to [***] of Intel's and
its Subsidiaries' Net Sales of Rambus Memories made by or
for Intel or its Subsidiaries, provided that for each
calendar quarter in which Intel ships at least five million
(5,000,000) Compatible integrated circuits that control PC
main memory, the royalty rate for that quarter shall be
reduced to [***] of Intel's and its Subsidiaries' Net Sales
of Rambus Memories made by or for Intel or its Subsidiaries.
(c) Modules, Boards, and Systems. During each quarter Net Sales
----------------------------
for each Rambus Memory incorporated into a Rambus Module,
Rambus Board, or Rambus System made by or for Intel shall be
calculated based on the average gross selling price earned
by Intel during such quarter on Sales of that Rambus Memory
made by or for Intel as components to unaffiliated customers
in arm's length sales. If there are no such Sales, then the
Parties shall use such average gross selling price of Rambus
Memories with similar functionality. Such royalties shall be
due upon the internal transfer of the Rambus Memory for such
incorporation.
(d) Nonmarket Dispositions. In the event that Rambus Memories
----------------------
made by or for Intel are Sold in circumstances in which the
selling price is established on other than an arms length
basis, Net Sales for each such Rambus Memory shall be
calculated based on the volume of such Rambus Memory
multiplied by the average gross selling price earned by
Intel during such quarter on Sales of that Rambus Memory to
unaffiliated customers in arm's length Sales. If there are
no such Sales, then the Parties shall use such average gross
selling price of Rambus Memories with similar functionality.
(e) Finished Products. Intel understands and agrees that
-----------------
royalties are to be paid hereunder for, and the royalty
rates specified herein are based upon, Net Sales of Rambus
Memories made by or for Intel in finished product form. If
Intel Sells Rambus Memories in unfinished form (e.g., as
processed wafers, unpackaged products, or otherwise
requiring additional work), then Net Sales for each such
Rambus Memory shall be calculated based on the volume of
such Rambus Memory multiplied by the average gross selling
price earned by Intel during such quarter on Sales of that
Rambus Memory, in finished product form, to unaffiliated
customers in arm's length Sales. If there are no such Sales,
then the Parties shall use the average selling price of
finished Rambus Memories with similar functionality.
5.3 Payments and Accounting.
-----------------------
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[*] Confidential treatment requested.
(a) Records and Audits. The Parties agree that an independent
------------------
accounting firm designated by Rambus and approved by Intel
(such approval not to be unreasonably withheld or delayed)
shall have the right to conduct audits of Intel for the
purpose of determining the accuracy of royalty payments
hereunder. In this regard, Intel agrees to maintain
sufficient production and sales records for Rambus Memories
and Rambus Logic Chips and to provide Rambus' designated
independent accounting firm with reasonable access to such
records. This provision will survive the termination of this
Agreement for a period of two (2) years. Audits shall be
conducted not more than once a year unless the preceding
audit revealed a discrepancy, and in each case during normal
business hours. Prompt adjustment shall be made by Intel to
compensate for any errors and/or omissions disclosed by such
examination or audit which result in an underpayment of
royalties hereunder. Should the amount of any such error
and/or omission exceed five percent (5%) of the total
royalties due for the period under audit, then upon written
request by Rambus, Intel shall pay for the cost of the
audit.
(b) Reports and Payment Terms. Within sixty (60) days after the
-------------------------
end of each calendar quarter, Intel shall furnish to Rambus
a statement in suitable form showing all Rambus Memories, by
part number, subject to royalties which were sold, leased,
or otherwise disposed of during the preceding calendar
quarter, and the royalty rate and amount of royalty payable
thereon. If no Rambus Memories subject to royalty have been
sold, leased, or otherwise disposed of, that fact shall be
shown on such statement. Also within this sixty (60) day
period, Intel shall pay to Rambus the Rambus Memory
royalties payable hereunder for such quarter. All royalty
and other payments to Rambus hereunder shall be in United
States dollars. Royalties based on Rambus Memory sales in
other currencies shall be converted to United States dollars
according to the rate of exchange for that currency as
quoted by the Wall Street Journal on the last publication
day of the calendar month in which the royalty accrued.
5.4 Royalties to Intel.
------------------
(a) In consideration of the engineering contributions of Intel
pursuant to this Agreement and the license granted to Rambus
in Section 3.1 above, Rambus agrees that during the term of
this Agreement, commencing with the second calendar quarter
of 1998 and until termination of Intel's royalty obligation
pursuant to Section 5.2(a) above, if in any calendar quarter
greater than twenty percent (20%) of Intel's shipments, by
unit volume, of integrated circuits that control main memory
are Compatible, then for that calendar quarter, for each
Rambus DRAM licensee whose sales of Rambus DRAMs are greater
than twenty-five percent (25%) of such licensee's total DRAM
sales for that quarter, on a unit volume basis, Rambus will
pay to Intel a royalty share equal to all amounts received
by Rambus as royalties from that licensee for that quarter
in excess of two percent (2%) (the "Reference Rate") of that
licensee's Net Sales of Rambus DRAMs. These royalties shall
be payable, reported,
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and subject to audit by Intel in accordance with the
procedures specified in Section 5.3 above, as applied to
Rambus as the payor and Intel as the payee, provided that
Rambus shall not be obligated to provide a royalty report
for any quarter if no royalty is payable for that quarter,
and provided further that it is understood that the
information permitting Rambus to determine whether a
particular licensee's sales of Rambus DRAMs exceed
twenty-five percent (25%) of such licensee's total sales of
DRAMs may not be available to Rambus until some time after
the end of the quarter, and Rambus shall not be obligated to
make any royalty payment until it is able to confirm this
information. In addition, Rambus' obligations pursuant to
this section shall be conditioned on Intel's having advised
Rambus, within thirty (30) days after the end of the
calendar quarter, that greater than twenty percent (20%) of
Intel's shipments of integrated circuits that control main
memory were Compatible. Rambus shall be entitled to audit
each such report in accordance with the procedures specified
in Section 5.3(a), provided that Rambus shall be limited to
one such audit per quarter.
(b) The Reference Rate of two percent (2%) specified in Section
5.4(a) above may be reduced only under the following
conditions: Intel shall meet annually with Rambus, during
which meeting Intel will provide its reasonable, good faith
projection of its requirements for system memory bandwidth
and memory size over the following three (3) to five (5)
years, and Rambus will provide its reasonable, good faith
projection of its memory subsystem interface bandwidth for
the same three (3) to five (5) years. Each Party will
provide to the other Party the underlying assumptions and
applicable data so that the other Party can independently
verify these projections. If, based upon the meeting, Intel
reasonably determines that its memory bandwidth requirements
for the next three (3) to five (5) years exceed what may be
reasonably expected from evolutionary improvements to the
Rambus-D Interface Technology, Intel shall so notify Rambus
in writing, including an explanation of the reason for
Intel's determination. If Intel does so notify Rambus in
writing, such notice shall include Intel's written
commitment to assign an appropriately staffed team of
engineers to work with Rambus to provide system architecture
tradeoff guidance to Rambus, then:
(i) If, within three (3) months after Intel's notification
and commitment of the above-referenced team of Intel
engineers, Rambus commences and continues to use its
reasonable best efforts to develop new, [***]
interface technology, reasonably designed to meet
Intel's specified future memory bandwidth requirements
with reasonable economics, then the Reference Rate
shall not be adjusted. For this purpose, "reasonable
best efforts" means Rambus' assignment of a development
team of appropriate size and skill reasonably designed
to achieve these objectives; or
(ii) If, within three (3) months after Intel's notification
and commitment of the above-referenced team of Intel
engineers,
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[*] Confidential treatment requested.
Rambus has not commenced using its reasonable best efforts
as described in paragraph (i) above, then, commencing in the
following calendar quarter, the Reference Rate will diminish
by one eighth (1/8) of one percent (1%) each quarter for
eight (8) quarters, until the Reference Rate is reduced to
one percent (1%). If, however, at any time thereafter Rambus
commences reasonable best efforts to develop the [***]
interface technology, as described in paragraph (i) above,
then the Reference Rate reduction shall cease and,
commencing with the first calendar quarter thereafter, the
Reference Rate shall increase by one eighth (1/8) of one
percent (1%) per quarter until it is again two percent (2%).
If, after having commenced reasonable best efforts, Rambus
ceases such reasonable best efforts, then the Reference Rate
will diminish as set forth above. In no event shall the
Reference Rate be less than one percent (1%) or more than
two percent (2%).
5.5 Warrant and Board Rights.
------------------------
(a) Within sixty (60) days after the Effective Date, Rambus
agrees to issue to Intel a warrant in the form attached
hereto as Exhibit E.
(b) Within sixty (60) days after the Effective Date, Rambus
shall deliver to Intel for Intel's signature, a fully
executed (except for Intel's signature) "Rambus Inc. Amended
and Restated Information and Registration Rights Agreement"
in the form attached hereto as Exhibit F.
5.6 Certain Transactions.
--------------------
(a) For purposes of this section, the following terms shall have
the following meanings:
(i) "Applicable Transaction" means any transaction between
Rambus and a third party after which:
(A) the third party would own, directly or indirectly,
beneficially or of record, voting securities
representing more than fifty percent (50%) of the
total voting power (a "Majority Interest") of
Rambus, unless persons previously owning a Majority
Interest of Rambus continue to own a Majority
Interest of such third party;
(B) Rambus would become a Party to a merger with the
third party in which Rambus is not the surviving
corporation, unless persons previously owning a
Majority Interest of Rambus continue to own a
Majority Interest of such surviving corporation; or
(C) Rambus would transfer all or substantially all of
its business and assets to the third party, unless
persons
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[*] Confidential treatment requested.
previously owning a Majority Interest of Rambus
continue to own a Majority Interest of such
transferee.
(ii) "Competitive" as applied to an Intel offer compared to
a third party offer means (A) the Intel offer includes
money and other consideration at least equal to the
money and other consideration included in the third
party offer, (B) the other terms and conditions of the
Intel offer are at least as favorable to Rambus as the
other terms and conditions of the third party offer,
and (C) the Intel offer is fully authorized by Intel
and shall constitute a binding agreement upon its
acceptance by Rambus.
(b) Rambus agrees to notify Intel in writing within five (5)
business days after Rambus commences negotiations to enter
into any Applicable Transaction with any third party. Intel
agrees to hold such information in strict confidence, to
refrain from trading in any publicly traded stock based on
such information, and to use such information solely for the
purpose of considering and making a competing offer to
Rambus. Rambus further agrees:
(i) to consider, in good faith, competing offers by Intel
to enter into an Applicable Transaction with Intel,
and
(ii) not to enter into any Applicable Transaction with any
third party until sixty (60) days after providing to
Intel the written notice required by this Section
5.6(b), but only if Intel has indicated to Rambus, in
writing within fifteen (15) days of such notice, that
it will be making a good faith effort to submit a
competing offer to enter into an Applicable
Transaction with Rambus.
(iii) If, prior to agreeing to enter into the Applicable
Transaction with the third party, Intel has made to
Rambus a Competitive bona fide offer to enter into an
Applicable Transaction with Intel, and,
notwithstanding such Competitive offer Rambus
consummates the Applicable Transaction with the third
party, then (A) Intel's royalty obligation pursuant to
Section 5.2(a)(i) shall cease as to Sales of Rambus
Logic Chips after the consummation of the Applicable
Transaction, (B) the license granted in Section 2
shall be fully paid, irrevocable, and survive
termination of this Agreement, and (C) Rambus shall
refund to Intel fifty percent (50%) of royalties paid
by Intel for Rambus Logic Chips pursuant to Section
5.2(a)(i) above, provided, however, such refund shall
be limited to a maximum of [***].
(c) After thirty (30) months after the Success Determination
Date, if less than twenty percent (20%) of Intel's
shipments, by unit volume, of integrated circuits that
control main memory are Compatible for any four (4)
consecutive calendar quarters, then the rights granted to
Intel under this Section 5.6 shall terminate.
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[*] Confidential treatment requested.
SECTION 6
6. CONFIDENTIAL INFORMATION
------------------------
6.1 Confidential Information. The term "Confidential Information"
------------------------
shall mean any information disclosed by one Party to the other
during the term of this Agreement, with regard to this
Agreement or otherwise, which is in written, graphic, machine
readable or other tangible form and is marked "Confidential",
"Proprietary" or in some other manner to indicate its
confidential nature. Confidential Information may also include
oral information disclosed by one Party to the other pursuant
to this Agreement, provided that such information is
designated as confidential at the time of disclosure and
reduced to a written summary by the disclosing Party, within
thirty (30) days after its oral disclosure, which is marked in
a manner to indicate its confidential nature and delivered to
the receiving Party. Notwithstanding any failure to so
identify it, however, (i) the Rambus Interface Technology
shall be deemed Rambus "Confidential Information" hereunder,
and (ii) technical information disclosed by Intel to Rambus
during the activities specified in Section 4.1 above shall be
deemed Intel "Confidential Information" hereunder, provided,
however, that in the event of controversy the burden of
proving that such information is truly confidential shall be
on the Party failing to identify it as such.
6.2 Confidentiality. Each Party shall treat as
---------------
confidential all Confidential Information of the other Party,
shall not use such Confidential Information except as
expressly set forth herein or otherwise authorized in writing,
shall implement reasonable procedures to prohibit the
disclosure, unauthorized duplication, misuse or removal of the
other Party's Confidential Information and shall not disclose
such Confidential Information to any third party, except as
set forth in Section 6.3 below. With respect to disclosures to
mutually agreed-upon third parties, Intel and Rambus shall
agree on the content of such disclosures provided, however,
that such third parties are under obligations of
confidentiality to Intel and Rambus. Such obligations may
include joint non-disclosure agreements among Intel, Rambus
and the third parties. Without limiting the foregoing, each of
the Parties shall use at least the same procedures and degree
of care which it uses to prevent the disclosure of its own
Confidential Information of like importance to prevent the
disclosure of Confidential Information disclosed to it by the
other Party under this Agreement, but in no event less than
reasonable care.
6.3 Disclosures to DRAM Companies.
-----------------------------
Intel shall be entitled to disclose Rambus Confidential
Information to third party DRAM companies which are
considering using Rambus Interface Technology, or which are
commencing implementation of Rambus Interface Technology, only
to assist such companies to get to market quickly with Rambus
DRAMs, and only if all of the following conditions are
satisfied:
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(a) The third party must be either (i) a company licensed by
Rambus to make and sell Rambus DRAMs pursuant to an
agreement which imposes upon the third party
confidentiality obligations with respect to Rambus
Confidential Information, or (ii) a DRAM company which
Intel believes, in good faith, intends to enter into a
license agreement with Rambus to make and sell Rambus
DRAMs, after evaluation of the Rambus technology, and
which is a party to a confidentiality agreement with
Rambus which, in Rambus' reasonable opinion, is adequate
to protect the type of Rambus Confidential Information
which Intel will disclose.
(b) Intel must be a party to a confidentiality agreement with
the third party pursuant to which disclosures by Intel of
Rambus Confidential Information are subject to the same
restrictions and obligations as are disclosures of Intel
Confidential Information.
(c) Rambus, Intel, and the third party must have entered into
a three-party confidentiality agreement that provides
that any Rambus Confidential Information disclosed to the
third party must be treated by the third party as if
Rambus had disclosed the Rambus Confidential Information
pursuant to Rambus' two-party confidentiality agreement
with the third party. Rambus will not unreasonably refuse
to enter into such a three-party agreement.
6.4 Exceptions. Notwithstanding the above, neither
----------
Party shall have liability to the other with regard to any
Confidential Information of the other which:
(a) was generally known and rightfully available at the time
it was disclosed or becomes generally known and
rightfully available through no fault of the receiver;
(b) was rightfully known to the receiver, without
restriction, at the time of disclosure as shown by the
files of the receiver in existence at the time of
disclosure;
(c) is disclosed with the prior written approval of the
discloser;
(d) was independently developed by the receiver without any
use of the Confidential Information by employees or other
agents of the receiver who have not been exposed to the
Confidential Information, provided that the receiver can
demonstrate such independent development by documented
evidence prepared contemporaneously with such independent
development; or
(e) becomes known to the receiver, without restriction, from
a source other than the discloser without breach of this
Agreement by the receiver and otherwise not in violation
of the discloser's rights.
(f) In addition, each Party shall be entitled to disclose the
other Party's Confidential Information to the extent such
disclosure is required by the
-22-
order or requirement of a court, administrative agency,
or other governmental body, provided that the Party
required to make the disclosure shall provide prompt,
advance notice thereof to enable the other Party to seek
a protective order or otherwise prevent such disclosure.
6.5 CNDA. The CNDA is hereby terminated and superseded by
----
this Agreement. All "Confidential Information" disclosed
pursuant to the CNDA shall be deemed Confidential Information
pursuant to this Section 6.
6.6 Residuals. Each Party may use Residuals for any
---------
purpose including, without limitation, use in development,
manufacture, promotion, sale and maintenance of its products
and services, provided that this right to Residuals does not
represent a license under any patents, copyrights, mask work
rights or other similar intellectual property rights of the
disclosing Party. The term "Residuals" means any information
that is retained in the unaided memories of the receiving
Party's employees who have had access to the disclosing
Party's Confidential Information pursuant to the terms of this
Agreement. An employee's memory is unaided if the employee has
not intentionally memorized the Confidential Information for
the purpose of retaining and subsequently using or disclosing
it.
SECTION 7
7. INTELLECTUAL PROPERTY OWNERSHIP, LICENSE TO RAMBUS AND
------------------------------------------------------
INDEMNIFICATION DISCLAIMER
--------------------------
7.1 Ownership.
---------
(a) Subject to the licenses granted to Intel herein, Rambus
shall own all right, title and interest in the Rambus
Interface Technology and all upgrades, enhancements and
improvements thereto made by Rambus. Subject to the
provisions of Section 4.3 above, Rambus shall own exclusive
distribution and content control of the Rambus-D Interface
Specification and may publish therein any contribution to
the Rambus-D Interface Technology by Intel consistent with
the licenses from Intel in Section 3 above, and Intel hereby
assigns, and agrees to assign, to Rambus the copyright in
any such Intel contribution. Except for Joint Developments,
each Party shall own the Developments that it solely makes.
(b) All Joint Developments shall be jointly and equally owned by
Intel and Rambus, and each Party shall be entitled to use
and exploit each such jointly owned Joint Development
without notice or accounting to the other Party. The Parties
shall confer and reasonably cooperate with respect to patent
and other intellectual property applications, filings and
registrations with respect to jointly owned Joint
Developments. For Joint Developments, patent expenses shall
be divided equally between the Parties provided that either
Party may elect not to share the expenses of
-23-
the patent application in any or all countries, in which
case the other Party may file at its own expense and shall
have sole control of prosecution thereof. For those Joint
Developments which principally read on general integrated
circuit structures and processes, Intel will have the first
option to control the application process. For those Joint
Developments which principally read on Rambus-D designs,
Rambus will have the first option to control the application
process.
(c) Both Parties agree that prior to July 1, 1996, there has
been no Joint Development in the Rambus-D Interface
Technology protocol area, and that prior to the Effective
Date, there has been no Joint Development in other areas of
Rambus-D Interface Technology.
7.2 Rambus Indemnification Disclaimer. Rambus disclaims and
---------------------------------
shall have no obligation of defense, contribution, or indemnity
with respect to any actual or alleged intellectual property
infringement with respect to the Rambus Interface Technology,
Rambus-1 Interface Specification, Rambus-D Interface
Specification, or otherwise arising out of this Agreement. Rambus
shall have no liability arising out of any such actual or alleged
intellectual property infringement. Intel, however, shall
promptly notify Rambus, in writing, of each such infringement
claim of which Intel becomes aware, and Intel shall cooperate
with Rambus if Rambus desires to intervene in any such
infringement action against Intel.
7.3 Intel Indemnification Disclaimer. Intel disclaims and shall
--------------------------------
have no obligation of defense, contribution, or indemnity with
respect to any actual or alleged intellectual property
infringement with respect to the Applicable Intel Intellectual
Property Rights or otherwise arising out of this Agreement. Intel
shall have no liability arising out of any such actual or alleged
intellectual property infringement. Rambus, however, shall
promptly notify Intel, in writing, of each such infringement
claim of which Rambus becomes aware, and Rambus shall cooperate
with Intel if Intel desires to intervene in any such infringement
action against Rambus.
SECTION 8
8. LIMITATION OF LIABILITY
-----------------------
IN NO EVENT SHALL EITHER PARTY BE LIABLE FOR ANY SPECIAL,
CONSEQUENTIAL, INDIRECT, OR INCIDENTAL DAMAGES, HOWEVER CAUSED, ON ANY
THEORY OF LIABILITY AND WHETHER OR NOT SUCH PARTY HAS BEEN ADVISED OF
THE POSSIBILITY OF SUCH DAMAGES, ARISING IN ANY WAY OUT OF THIS
AGREEMENT OR THE DESIGNS, TECHNOLOGY OR PRODUCTS LICENSED OR OTHERWISE
PROVIDED PURSUANT TO THIS AGREEMENT. IN NO EVENT WILL RAMBUS' LIABILITY
ARISING OUT OF THIS AGREEMENT EXCEED THE FEES, ROYALTIES, AND OTHER
AMOUNTS RECEIVED BY RAMBUS HEREUNDER. IN NO EVENT WILL INTEL'S
LIABILITY ARISING OUT OF THIS AGREEMENT EXCEED THE FEES, ROYALTIES, AND
OTHER AMOUNTS PAID OR
-24-
PAYABLE BY INTEL HEREUNDER, PROVIDED, HOWEVER, THAT THIS MAXIMUM
LIABILITY OF INTEL SHALL BE IN ADDITION TO INTEL'S OBLIGATION TO PAY
ALL FEES, ROYALTIES, AND OTHER AMOUNTS PAYABLE, BUT UNPAID, BY INTEL.
THESE LIMITATIONS, HOWEVER, SHALL NOT APPLY TO INFRINGEMENT OF THE
OTHER PARTY'S INTELLECTUAL PROPERTY RIGHTS OR BREACHES OF SECTION 6
HEREOF.
SECTION 9
9. TERM AND TERMINATION
--------------------
9.1 Term. The term of this Agreement shall commence as of
----
the Effective Date and, unless and until terminated hereunder,
shall continue until the expiration of the last to expire
Rambus patent within the Rambus Intellectual Property Rights.
9.2 Termination.
-----------
(a) Intel shall be entitled to terminate this Agreement, at any
time, on written notice to Rambus.
(b) Rambus, at its option, may, in addition to any other
remedies it may have, terminate this Agreement on written
notice to Intel if:
(i) Intel defaults in the performance of any payment
obligations hereunder and if any such default is not
corrected within forty-five (45) days after Intel
receives written notice thereof from Rambus;
(ii) Intel breaches Section 2.1 or Section 2.2 above;
(iii) At thirty (30) months after the Success Determination
Date unless in any two prior consecutive calendar
quarters, twenty percent (20%), by unit volume, of
integrated circuits shipped by Intel that directly
control main memory were Compatible;
(iv) at any time between January 15, 1997 and the Success
Determination Date, Intel communicates to any of the
then current top ten (10) DRAM manufacturers that Intel
has plans to support, as the primary DRAM for PC main
memory applications for the years 2000, 2001 and 2002,
any New Interface other than the Rambus-D Interface
Technology; or
(v) at any time between January 15, 1997 and the Success
Determination Date, the Intel senior member attending
the quarterly Rambus/Intel executive meeting, upon
Rambus' request, does not represent to the Rambus
officers attending such meeting that the Rambus-D DRAM
will be the primary DRAM for PC main memory
applications for the years 2000, 2001 and 2002.
-25-
(i) For purposes of this Subsection (b), "New Interface" means
any interface for PC main memory applications, other than
main memory interfaces on IntelOs chipsets shipped prior to
the second calendar quarter of 1998, and evolution of such
main memory interfaces extending therefrom. Any DRAM
interface which provides greater than one (1)
Gigabyte/second/device bandwidth is considered a New
Interface.
9.3 Survival.
--------
(a) Upon any termination or expiration of this Agreement, then,
except as set forth in Section 5.2(a)(ii) above and Section
9.3(b) below, all licenses and rights granted by Rambus shall
terminate, and except as required by Intel to exercise those
rights surviving pursuant to Section 9.3(b) below, Intel shall
promptly destroy or deliver to Rambus all materials comprising,
incorporating, or using any Rambus Interface Technology,
Confidential Information, or Rambus Intellectual Property Rights.
In addition, all amounts due or payable to Rambus or Intel as a
result of events prior to the effective date of termination or
expiration shall remain due and payable. The provisions of
Sections 2.1(c), 2.5, 3 (provided that Rambus' rights pursuant to
Section 3.1 shall be limited to those Intel patents and patent
applications entitled to a first effective filing date prior to
the effective date of termination of this Agreement, and to those
copyrights, trade secrets and other intellectual property rights
(other than mask work rights) in existence as of the effective
date of termination), 4.7, 4.8, 5.3, 5.4 (as to the Parties'
audit rights only), 6 (as to Confidential Information disclosed
prior to termination of this Agreement), 7, 8, 9.3, 10, and 11
(excluding paragraphs (f)(i) through (f)(iv) of Section 11.1)
shall survive any expiration or termination of this Agreement for
any reason.
(b) Upon termination of this Agreement by Intel pursuant to Section
9.2(a) above:
(i) Intel shall retain the right, pursuant to Section 2.1(a)(i)
above, to Sell (but not to design, make, or have made)
Rambus ICs made by or for Intel prior to the effective date
of termination of this Agreement. Sales of Rambus Memories
pursuant to this section shall be subject to Sections 5.2
(excluding Section 5.2(a)) and 5.3.
(ii) If by twelve months following the Success Determination Date
or, if earlier, by the effective date of termination of this
Agreement, for more than any two consecutive calendar
quarters more than twenty percent (20%) of Intel's sales, by
unit volume, of integrated circuits that directly control
main memory were Compatible, then Intel's license pursuant
to Section 2.1(a)(ii) shall survive at no charge to Intel,
provided that this license will be limited to those Rambus
patents and patent applications entitled to a first
effective filing date prior to the effective date of
-26-
termination of this Agreement, and shall be limited to those
copyrights, trade secrets, and other intellectual property
rights in existence as of the effective date of termination.
SECTION 10
10. GOVERNING LAW AND ARBITRATION
-----------------------------
10.1 Governing Law. This Agreement shall be governed by and interpreted in
-------------
accordance with the laws of the State of New York, without reference
to conflict of laws principles.
10.2 Arbitration. Any dispute or claim arising out of or in connection
-----------
with this Agreement shall be finally settled by binding arbitration in
Palo Alto, California under the Commercial Rules of Arbitration of the
American Arbitration Association by one arbitrator appointed in
accordance with said rules. The arbitrator shall apply New York law
to the merits of any dispute or claim, without reference to rules of
conflicts of law or arbitration. Judgment on the award rendered by
the arbitrator may be entered in any court having jurisdiction
thereof. Notwithstanding the foregoing, the Parties may apply to any
court of competent jurisdiction for injunctive relief without breach
of this arbitration provision. Prior to initiating arbitration or
litigation, however, senior executives of the Parties shall meet to
attempt to resolve the dispute or claim. If a Party requests such a
meeting but the other Party does not make a senior executive available
for the meeting within ten (10) days after the request, then the
requesting Party shall then be entitled to initiate arbitration (or,
as applicable, litigation). Prior to initiating a meeting, dispute,
claim or litigation, the initiating Party shall provide to the other
Party a written description of the points of dispute or claim arising
under the express terms of this Agreement.
10.3 Equitable Relief. Notwithstanding the provisions of Section 10.2
----------------
above, a Party shall have the right, without the requirement of first
seeking a remedy through arbitration, to seek temporary or preliminary
injunctive or other equitable relief in any proper court in the
event that Party determines that redress through arbitration will not
provide a sufficient temporary or preliminary remedy for any violation
by the other Party of its obligations regarding Confidential
Information of the Party bringing the equitable relief action under
this Agreement. Each Party agrees that such injunctive or other
equitable relief will be a necessary and proper remedy in the event of
misuse or disclosure by such Party of the other Party's Confidential
Information.
SECTION 11
11. MISCELLANEOUS
-------------
-27-
11.1 Confidentiality of Agreement. Each Party agrees that this Agreement
----------------------------
and the terms and conditions of this Agreement shall be treated as
Confidential Information and that neither Party will disclose this
information to any third party without the prior written consent of
the other Party, provided, however, that each Party may disclose this
information:
(a) as required by any court or other governmental body;
(b) as otherwise required by law;
(c) to legal counsel of the Parties, accountants, and other
professional advisors;
(d) in confidence, to banks, investors and other financing sources
and their advisors; and
(e) in confidence, in connection with an actual or prospective merger
or acquisition or similar transaction.
(f) In addition:
(i) Rambus shall be entitled to communicate to DRAM companies
that it is working with Intel to jointly define the Rambus-
D Interface Specification, which may include co-support for
the Rambus-1 Interface Specification and the Rambus-D
Interface Specification if this can be accomplished without
unreasonably compromising development of the Rambus-D
Interface Specification.
(ii) Intel may communicate to DRAM and memory component
companies (A) Intel's intention to produce PC main memory
control chipsets Compatible with the Rambus-D Interface
Specification and (B) details of Intel's rights pursuant to
Section 5.4 above.
(iii) Not later than early in the first calendar quarter of 1997,
Intel shall advise all DRAM suppliers with which Intel is
then currently working of Intel's intention to produce PC
main control chipsets Compatible with the Rambus-D
Interface Specification, with corresponding Compatible DRAM
mass production required starting in the [***].
(iv) In any initial public offering of Rambus' stock, Intel and
Rambus will agree upon a common message with respect to
this Agreement to analysts and investors that complies with
Securities and Exchange Commission requirements of public
disclosure of material information. Subject to the
foregoing, it is currently anticipated that the message to
analysts and investors will be that Intel has entered into
a strategic agreement with Rambus that is proceeding with
respect to development of the Rambus-D
-28-
[*] Confidential treatment requested.
Interface Specification [***].
11.2 Assignment. Neither Party may assign or delegate this Agreement or
----------
any of its licenses, rights or duties under this Agreement, by
operation of law or otherwise, without the prior written consent of
the other Party, except Rambus may assign this Agreement to a person
or entity into which it has merged or which has otherwise succeeded
to all or substantially all of its business and assets, and which has
assumed in writing or by operation of law its obligations under this
Agreement. Any assignment in violation of this section shall be void.
In the event of any such assignment or attempted assignment by Intel,
this Agreement and all rights and licenses granted to Intel shall
automatically terminate.
11.3 Authority. Each Party represents that all corporate action necessary
---------
for the authorization, execution and delivery of this Agreement by
such Party and the performance of its obligations hereunder has been
taken.
11.4 Notices. All notices required or permitted hereunder shall be in
-------
writing and shall be mailed by registered or certified mail, postage
prepaid, or otherwise delivered by hand, by messenger or by
telecommunication, addressed to the addresses first set forth above
or at such other address furnished with a notice in the manner set
forth herein. Such notices shall be deemed to have been served when
delivered or, if delivery is not accomplished by reason of some fault
of the addressee, when tendered.
11.5 Intel Technical Contact. Intel hereby designates [***] as the
-----------------------
Intel Technical Contact for this Agreement. Intel may change the
Intel Technical Contact by notice to Rambus as provided for In
Section 11.4, above.
11.6 Export Controls. Each Party agrees to comply with all U.S. export
---------------
regulations in connection with this Agreement.
11.7 Counterparts. This Agreement may be executed in two (2) or more
------------
counterparts, all of which, taken together, shall be regarded as one
and the same instrument.
11.8 Partial Invalidity. If any paragraph, provision, or clause thereof in
------------------
this Agreement shall be found or be held to be invalid or
unenforceable in any jurisdiction in which this Agreement is being
performed, the remainder of this Agreement shall be valid and
enforceable and the Parties shall negotiate, in good faith, a
substitute, valid and enforceable provision which most nearly effects
the Parties' intent in entering into this Agreement.
11.9 Relationship of Parties. The Parties hereto are independent
-----------------------
contractors. Nothing contained herein or done in pursuance of this
Agreement shall constitute either Party the agent of the other Party
for any purpose or in any sense whatsoever, or constitute the Parties
as partners or joint venturers.
11.10 Modification. No alteration, amendment, waiver, cancellation or any
------------
other change in any term or condition of this Agreement shall be
valid or binding on
-29-
[*] Confidential treatment requested.
either Party unless the same shall have been mutually assented to in
writing by both Parties.
11.11 Waiver. The failure of either Party to enforce at any time the
------
provisions of this Agreement, or the failure to require at any time
performance by the other Party of any of the provisions of this
Agreement, shall in no way be constituted to be a present or future
waiver of such provisions, nor in any way affect the right of either
Party to enforce each and every such provision thereafter. The
express waiver by either Party of any provision, condition or
requirement of this Agreement shall not constitute a waiver of any
future obligation to comply with such provision, condition or
requirement.
11.12 Force Majeure.
-------------
(a) If the performance of this Agreement or any obligations
hereunder, other than the payment of money, is prevented,
restricted or interfered with by reason of fire or other casualty
or accident, strikes or labor disputes, war or other violence,
any law, order, proclamation, regulations, ordinance, demand or
requirement of any government agency, or any similar act or
condition beyond the reasonable control of the Parties hereto
("Event of Force Majeure"), the Party so affected upon giving
prompt notice to the other Party shall be excused from such
performance to the extent of such prevention, restriction or
interference; provided that the Party so affected shall use its
reasonable best efforts to avoid or remove such causes of
nonperformance and shall continue performance hereunder with the
utmost dispatch whenever such causes are removed.
(b) The Party suffering an Event of Force Majeure shall notify the
other Party within fifteen (15) days of the occurrence of such
Events and within thirty (30) days shall furnish the other Party
with a recovery plan of action. Without limiting the foregoing, a
Party suffering an Event of Force Majeure shall use its
reasonable best efforts to limit the impact of the Event of Force
Majeure on such Party's performance of this Agreement.
11.13 Section Headings. The section headings contained in this
----------------
Agreement are for reference purposes only and shall not affect in
any way the meaning or interpretation of this Agreement.
11.14 Prior Agreement. The Prior Agreement is hereby terminated and
---------------
superseded by this Agreement. Except for liability for breach of the
Prior Agreement during its term, and notwithstanding Sections 9.3 and
11 of the Prior Agreement, the Parties shall have no rights,
obligations, or liability arising out of the Prior Agreement. As of
the Effective Date of this Agreement, Confidential Information
subject to Section 6 of the Prior Agreement shall be deemed
Confidential Information subject to Section 6 of this Agreement.
11.15 Entire Agreement. The terms and conditions herein contained
----------------
(including the exhibits attached hereto) constitute the entire
agreement between the Parties
-30-
and supersede all previous agreements and understandings, whether
oral or written, between the Parties hereto with respect to the
subject matter hereof.
IN WITNESS WHEREOF, the Parties hereto have caused this Agreement to be signed
by duly authorized officers or representatives as of the dates below written.
RAMBUS INC. INTEL CORPORATION
By: ____________________________ By: ______________________________
Name: __________________________ Name: ____________________________
Title: _________________________ Title: ___________________________
Date: __________________________ Date: ____________________________
-31-
EXHIBIT A
RAMBUS-1 INTERFACE TECHNOLOGY
-----------------------------
The Rambus-1 Interface Technology is a complete memory subsystem capable of
transferring data from 500 to 800 megabytes per second. The elements of the
Rambus-1 Interface Technology are shown within the dotted box in the following
diagram, and include the RMC, RAC, Channel, Sockets, Modules, the interface
portion of RDRAM, and associated clocking.
[DIAGRAM OF RAMBUS-1 INTERFACE APPEARS HERE]
-A-1-
The logic device (processor, peripheral, ASIC, etc.) contains the storage and
processing functions needed by the application (Application Units). The
application can access further storage in external Rambus DRAM (RDRAM)
components using the 9-bit Rambus Channel.
The RDRAM is manufactured with standard sub-micron CMOS. The Rambus Interface is
either on the edge of the die or centered in the case of LOC. Good parasitics
are maintained by this pin placement and small number of I/O. Advanced CMOS
circuit design techniques are used in the implementation of the driver/receiver
and clock circuitry of the Rambus Interface.
RDRAMs can be packaged in either horizontal or vertical packages. Packaged
RDRAMs can be directly soldered to the system board or soldered to modules for
memory expansion via a socket. Other RDRAM expansion techniques are possible.
The Rambus Channel runs at a data transfer rate of from 500 to 800 megabytes per
second. These transfer rates are maintained through sockets and large memory
subsystems.
The Rambus ASIC Cell (RAC) is the Input/Output cell which resides on the edge of
the die of the logic device. The RAC provides the basic
multiplexing/demultiplexing functions for converting from the off-chip byte-
serial bus with a 500 to 800 MHz data rate (Channel) to a wider, and slower, on-
chip bus. The RAC manages the physical layer of the Rambus subsystem.
The RMC manages the logical layer of the Rambus subsystem. The RMC sits between
the RAC and the Application Unit and provides a simple intermediate protocol for
performing read and write transactions to RDRAMs. The RMC also supports
interleaved transactions, permitting a RAS access to be started in one RDRAM
while a CAS access is performed to another. The RMC serves as a reference design
and it may be used as-is, or it may be modified for a particular application.
A much more complete description of the Rambus-1 Interface Technology at its
current state of development is contained in the public documents: Concurrent
RDRAM data sheet, RAC Users Guide and Specification, Rambus Memory Controller
manual, and Rambus Product Guide. Rambus Inc. is in the final stages of
development of the Rambus-1 Interface Technology, so material changes in
function or specification are possible and Rambus Inc. makes no representation
or warranty otherwise. It is agreed that Rambus-1 Interface Technology includes
all Rambus interface technologies prior to Rambus-D Interface Technology.
-A-2-
EXHIBIT B
RAMBUS-D INTERFACE TECHNOLOGY
------------------------------
The Rambus-D Interface Technology is a complete memory subsystem capable of
high speed memory transfer. The elements of the Rambus-D Interface Technology
are shown within the dotted box in the following diagram, and include the [***]
-B-1-
[*] Confidential treatment requested.
[***].
[***] Confidential Treatment Requested.
-B-2-
EXHIBIT C
TRADEMARKS
----------
Rambus, RDRAM, RModule, RSocket, and [R LOGO] are trademarks of Rambus Inc.
The required marking on each Licensed Rambus IC is: [R LOGO]
When using the Rambus Inc. trademarks in documentation and presentations, the
Rambus Licensee must follow the guidelines below:
1. The first occurrence of each of the trademarks in text needs to have the
superscript TM to notify the reader of the trademark. Subsequent occurrences in
the same document do not require the TM. This must be done for each trademark.
An example is:
The Rambus/(TM)/ DRAM is also referred to as an RDRAM
2. The Licensee must provide notice in each document of the Rambus trademarks
used and that they are trademarks of Rambus Inc. This notice would typically
accompany the Licensee's own trademark and copyright notices. If, for example,
the terms Rambus and RDRAM are used:
Rambus and RDRAM are trademarks of Rambus Inc.
3. When referring to Rambus as a company, use Rambus Inc. This usage does not
need a TM symbol, even if it is the only usage of the term Rambus.
4. Rambus should never be used as a noun, only as an adjective modifying a
noun. Examples of acceptable usage are:
the Rambus Channel
the Rambus Interface
the Rambus Standard
-C-1-
EXHIBIT D
ENGINEERING MILESTONES AND APPROXIMATE TIMELINE
-----------------------------------------------
[***]
-D-1-
[*] Confidential treatment requested.
