1024-Channel FDM CMOS ASIC (ASIC3 Sample Clauses

1024-Channel FDM CMOS ASIC (ASIC3. Based on the novel GFET frequency-domain multiplexing concept introduced in previous periodic reports, a full-custom mixed-signal ASIC capable of 1024-channel GFET FDM in a single low-power and compact chip. Figure 11 shows the modular architecture proposed for the frequency-domain multiplexing of 32x32 arrays of liquid-gate GFET sensors. It is worth to highlight here that the continuous-time FDM approach allows a real switch-less circuit implementation, with the corresponding benefits of glitch-free operation and the lack of current offset cancellation requirements. As it can be already noticed in Figure 11, the ASIC3 row current read-out channel is very similar to the one used in the ASIC2 TDM architecture of Figure 3, and so it is the digital interface to the corresponding FPGA module. On the other hand, a completely new circuit has been designed from scratch for the digital generation of the column harmonic carriers needed by FDM. The exact phase and frequency control of this harmonic generation is of key importance when optimizing the row ADC full-scale occupancy of the combined column carriers, as illustrated in the same Figure 11, where a 4-fold reduction factor of full scale is achieved at the summation of all the 32 FDM carriers. Figure 11: 1024-channel ASIC3 architecture proposal for the frequency-domain multiplexing of switch-less GFET sensor arrays in brain mapping. For a robust and fully tunable (in phase and frequency) digital harmonic generation, the column module architecture of Figure 12 has been finally integrated for each of the 16 column pairs of ASIC3. Basically, the I/Q carrier synthesis is performed in fourth steps. First, a 10-bit sinusoidal waveform of the exact wanted phase and frequency is built using a ¼-period digital look-up table. For the purpose of simplifying the later DAC circuit implementation, an oversampled multi-stage noise shaping (MASH) digital modulator is employed to translate this 10-bit synthesized waveform into a 7-level second-order Delta-Sigma modulated pulse stream, which preserves the wanted low- frequency harmonic contents but it pushes the large instantaneous quantization error power to the high-frequency region. Then, a simple 7-level flash resistive DAC can translate the pulse stream into the analog domain, so it can be processed by a third-order low-pass filter realized with OpAmp-RC CMOS circuits. Finally, proper analog buffers drive each continuous-time harmonic voltage carrier to the corresponding lo...