1024-Channel TDM CMOS ASIC (ASIC2 Sample Clauses

1024-Channel TDM CMOS ASIC (ASIC2. The classic TDM scheme of 2D arrays applied to GFET sensors is depicted in Figure 2(a), where each μECOG recording site incorporates a selection transistor (i.e. 2T cell). However, the alternative TDM approach of Figure 2(b) is chosen for ASIC2, being all GFET sensors permanently connected to their shared columns and rows of the array (i.e. 1T cell). In this scenario, channel multiplexing is controlled from the ASIC by changing the drain-source voltage biasing (VDS) of GFETs column wise. While all row lines are biased to ground (i.e. VDS ≡ 0) by the respective transresistance preamplifiers, the selection of a particular column of each row involves changing its column from ground to the activation level (i.e. VDS ≡ Vrefd), with typical values of Vrefd < 100mV. It is important to control the biasing of all columns even when they are not selected, since leaving them in high impedance would cause crosstalk currents flowing between rows. The proposed μECOG channel multiplexing method presents several advantages. First, the ambivalent conduction nature of the GFET sensor means in practice that another technology must incorporate the switching device (e.g. MOSFET) for the classic TDM of Figure 2(a), but all switches of Figure 2(b) are outside the flexible sensory array and located inside the CMOS ASIC, with the corresponding reductions in both technology complexity and integration costs. Second, the power consumption of the whole GFET array at any time is limited to 32 active devices only, so it scales with √Nch. Third, since the column-wise selection of the GFET active sensor does not involve drastic changes in its gate bias point, transient artifacts due to charge injection and clock feedthrough are attenuated and so are spurious signals. However, the active sensor multiplexing scheme of Figure 2(b) also introduces a couple of design challenges to be faced. The technology mismatching between GFETs of the sensory array belonging to the same row requires a programmable offset cancellation mechanism in order to subtract from Irow the individual DC current level of each channel, which must be fully covered by ASIC2. Also, when the size of the μECOG sensory array scales up, the reduction in impedance of each row degrades the input preamplifier noise figure, as fully explained later on, so some noise cancellation mechanism is also needed in ASIC2.