ATS9462 Sample Clauses

ATS9462. In 10 MHz PLL external clock mode, the ATS9462 can generate a sample clock between 150 and 180 MHz in 1 MHz steps from an external 10 MHz reference input. Sample data can be decimated by a factor of 1 to 100000. Call AlazarSetCaptureClock specifying EXTERNAL_CLOCK_10MHz_REF as the clock source, the desired sample rate between 150 and 180 MHz in 1 MHz steps, and the decimation factor. For example, the following code fragment shows how to generate a 15 MS/s sample rate with a 10 MHz external clock input. AlazarSetCaptureClock( handle, // HANDLE –- board handle EXTERNAL_CLOCK_10MHz_REF, // U32 –- clock source Id 150000000, // U32 –- sample rate Id or value CLOCK_EDGE_RISING, // U32 –- clock edge Id 10 // U32 –- decimation );