POET’s Unique Feature Sample Clauses

POET’s Unique Feature. A Seamless Low Power SoC-Design Flow System-on-Chip (SoC) design flows, as they are applied by many design companies, commonly start with a C/C++ executable specification of the system’s functionality. An in- depth analysis of the specification is carried out to get a rough estimate of the timing behaviour as well as area and power requirements. Based on these estimates, the system description is partitioned into software and hardware parts. The software parts are mapped onto processors and DSPs while the hardware part is synthesised to a gate level netlist. Timing and overall system cost are the driving metrics for this partitioning step. After partitioning, the POET low power optimisation methodology is applicable. This methodology will be realised by a set of new design tools. The software power optimisation flow transforms the software specification into a functional equivalent description. The resulting description is optimised with respect to the required energy consumption to execute on a given processor architecture including the memory sub-system. Traditional compilation finishes this part of the design flow. The hardware specification is optimised for its power consumption at two different levels of abstraction in order to benefit from all effective optimisation design tricks. At the algorithm level, the hardware specification is first transformed similar to the optimisation step at the software side. However, the hardware transformations have a different cost metric behind. These transformations are mainly interconnect driven because interconnect cost tend to dominate the overall hardware power cost. The second design step at the algorithm level is synthesis to the register transfer level of abstraction. This high-level synthesis task is supported by the POET design flow in that low power scheduling, allocation, and binding constraints are generated. Finally, fine-grained power optimisations at the RT level are performed which address communication interfaces, power management, and the memory hierarchy. Logic synthesis and place and route, being outside the scope of POET, are the remaining design steps.