Common use of Transformation Clause in Contracts

Transformation. The resulting Modest code comprises a parallel process at its highest level, which contains service “image processing service”, resources “CPU” and “GPU” that run forever, and two generators that call “image - processing service”. The service waits for incoming requests of either of the gen- erators and triggers the process, similar to the iDSL process, in return. Atomic processes in the process call the respective resources, which perform a delay. Since nondeterministic scheduling is employed, the resources have no queues. Evaluation. The iDSL measure (see Table 6) contains two measures, as follows. First, discrete-event simulation yields a single MODES execution that leads to latencies and utilizations in one go. Second, TA-based model checking includes rounding the real values to inte- gers. Since all but one values of the loads and rates are integers already, the model is not affected by this step. The uniform choice of atomic task “noise reduction”, however, is turned into a nondeterministic equivalent. Stopwatches are added to measure latencies. Given this model, a lower and upper bound latency are obtained via the binary search algorithm of Sect. 4.4 (TA-based model checking). Results come in various kinds, as follows. First, the latency bar chart for off- set = 0 of Fig. 11(c) conveys that the latencies vary much, i.e., between 200 and 380, as a result of extreme concurrency. This variation is less for other offsets. Second, the latency breakdown chart for offset = 0 of Fig. 11(a) illustrates how the overall latency is dispersed over its subprocesses. Tasks “Noise reduction” and “Contrast” account for 71% of the total latency. The utilization of “CPU” of 0.83 is high, but not alarming. The utilization of “GPU” is low, viz., 0.025. Third, the cumulative distribution graph of Fig. 11(b) displays the cumula- tive latency functions for seven designs with offsets varying from 0 to 200. As anticipated, the offsets and latency times are negatively correlated, i.e., a smaller offset induces that the execution of services overlap more (see Table 13) and thus display more concurrency. In turn, this leads to a higher latency. Fourth, Fig. 10 conveys, for a system with one service and obtained via TA-based model checking, the minimum and maximum absolute latency, viz., 159 and 189, respectively. It also shows a CDF of the same system based on discrete-event simula- tion. We observe that the bounds are valid, i.e., s(159) = 0 and s(189) = 1, and strict, i.e., s(159 + s) > 0 and s(189 − s) < 1,

Transformation. The resulting Modest code comprises a parallel process at its highest level, which contains service “image processing service”, resources “CPU” and “GPU” that run forever, and two generators that call “image - processing service”. The service waits for incoming requests of either of the gen- erators and triggers the process, similar to the iDSL process, in return. Atomic processes in the process call the respective resources, which perform a delay. Since nondeterministic scheduling is employed, the resources have no queues. Evaluation. The iDSL measure (see Table 6) contains two measures, as follows. First, discrete-event simulation yields a single MODES execution that leads to latencies and utilizations in one go. Second, TA-based model checking includes rounding the real values to inte- gers. Since all but one values of the loads and rates are integers already, the model is not affected affected by this step. The uniform choice of atomic task “noise reduction”, however, is turned into a nondeterministic equivalent. Stopwatches are added to measure latencies. Given this model, a lower and upper bound latency are obtained via the binary search algorithm of Sect. 4.4 (TA-based model checking). Results come in various kinds, as follows. First, the latency bar chart for off- off- set = 0 of Fig. 11(c) conveys that the latencies vary much, i.e., between 200 and 380, as a result of extreme concurrency. This variation is less for other offsetsoffsets. Second, the latency breakdown chart for offset offset = 0 of Fig. 11(a) illustrates how the overall latency is dispersed over its subprocesses. Tasks “Noise reduction” and “Contrast” account for 71% of the total latency. The utilization of “CPU” of 0.83 is high, but not alarming. The utilization of “GPU” is low, viz., 0.025. Third, the cumulative distribution graph of Fig. 11(b) displays the cumula- tive latency functions for seven designs with offsets offsets varying from 0 to 200. As anticipated, the offsets offsets and latency times are negatively correlated, i.e., a smaller offset offset induces that the execution of services overlap more (see Table 13) and thus display more concurrency. In turn, this leads to a higher latency. Fourth, Fig. 10 conveys, for a system with one service and obtained via TA-based model checking, the minimum and maximum absolute latency, viz., 159 and 189, respectively. It also shows a CDF of the same system based on discrete-event simula- tion. We observe that the bounds are valid, i.e., s(159) = 0 and s(189) = 1, and strict, i.e., s(159 + sϵ) > 0 and s(189 − sϵ) < 1,