Qualified Probed Wafer definition

Qualified Probed Wafer means a Qualified Probed Wafer with a unique Design ID that is completed at the Singapore Fab after the applicable Initial Joint Qualification Release.
Qualified Probed Wafer means a Probed Wafer with a unique Design ID utilizing a [***] Process Technology Node that is requested to be manufactured by the JDP Committee at the Singapore Fab. “[***] Pre-Qualified Probed Wafer Commitment” shall have the meaning set forth in Section 2.1(a)(ii). “[***] Pre-Qualified Probed Wafer Demand Forecast” shall have the meaning set forth in Section 3.1(a)(ii). “[***] Products” means Pre-Qualified Probed Wafers, Run at Risk Probed Wafers or Qualified Probed Wafers manufactured on the [***] Process Technology Node. “[***] Run at Risk Probed Wafer” means a Probed Wafer to be manufactured utilizing the [***] Process Technology Node that is requested to be started by Intel (but not requested to be started by the JDP Committee), and is started at the Singapore Fab before the [***] Initial Joint Qualification Release. “[***] Run at Risk Probed Wafer Demand Forecast” shall have the meaning set forth in Section 3.1(a)(iv).
Qualified Probed Wafer means a Probed Wafer with a unique Design ID utilizing a [***] Process Technology Node that is requested to be manufactured by JDP Committee at the Singapore Fab. “[***] Pre-Qualified Probed Wafer Commitment” shall have the meaning set forth in Section 2.1(a)(i). “[***] Pre-Qualified Probed Wafer Demand Forecast” shall have the meaning set forth in Section 3.1(a)(i). “[***] Run at Risk Probed Wafer” means a Probed Wafer to be manufactured utilizing the [***] Process Technology Node that is requested to be started by Intel (but not requested to be started by the JDP Committee), and is started at the Singapore Fab before the [***] Initial Joint Qualification Release. “[***] Run at Risk Probed Wafer Demand Forecast” shall have the meaning set forth in Section 3.1(a)(iii). “[***] Supplemental Supply Agreement” means the [***] Supplemental Supply Agreement, dated as of the Effective Date, by and among Intel, MSA and MTI. “[***] Base Run at Risk Probed Wafer Commitment” shall have the meaning set forth in Section 2.1(c). Exhibit A-1 “[***] Design ID Ready Date” means the date that the [***] that the first Design ID with respect to [***] Process Technology Node is ready to commence manufacture at the Singapore Fab. “[***] Incremental Run at Risk Probed Wafer Commitment” shall have the meaning set forth in Section 2.1(c).

Examples of Qualified Probed Wafer in a sentence

  • Intel will base the Qualified Probed Wafer Demand Forecast on Singapore Fab yield forecasts provided by Micron.

  • The Qualified Probed Wafer Demand Forecast will include desired Qualified Probed Wafer breakout by Design ID, Process Technology Node, process revision and probe test revision.

  • In addition, the Qualified Probed Wafer Demand Forecast will include the level of Probe Testing, marking specification and packaging requirements, requested delivery date and place of delivery for the Qualified Probed Wafers, which information will be updated by Intel on a weekly basis as necessary.

  • The Qualified Probed Wafer Demand Forecast will be [***] for the [***] and [***] thereafter.

  • The aggregate amount of Qualified Probed Wafers in each Qualified Probed Wafer Demand Forecast (and each update thereof) will be equal to at least an amount sufficient to permit Intel to satisfy the Qualified Probed Wafer Commitment for each Order Year covered in whole or in part by the applicable Qualified Probed Wafer Demand Forecast without the need to purchase more than [***] Qualified Probed Wafers [***] during such Order Year.

  • Intel will update the Qualified Probed Wafer Demand Forecast on a weekly or monthly basis, as needed, utilizing the demand planning process in effect between the Parties as of the Effective Date or as may be revised from time to time by mutual agreement of the Parties.

  • In each Response to Forecast, but subject to Section 3.1(b)(i), Micron will commit to supply quantities sufficient to satisfy the Qualified Probed Wafer Commitment.

  • If Micron furnishes Intel with a Response to Forecast that commits to supply quantities greater than the Qualified Probed Wafer Commitment in the Ramp Period or an Order Year, but no greater than the applicable Demand Forecast, then the Qualified Probed Wafer Commitment in the Ramp Period or that Order Year shall be deemed to be the greater amounts indicated in the Response to Forecast.

  • Within a period of time, not to exceed the lesser of the actual warranty period applicable to the end customer for the Qualified Probed Wafer at issue or [***] ([***]) months from the date of the delivery of the Qualified Probed Wafers at issue to Intel (the “Warranty Notice Period”), Intel shall notify Micron if it believes that any Qualified Probed Wafer does not meet the warranty set forth in Section 6.1. Intel shall return such Qualified Probed Wafers to Micron as directed by Micron.

  • In each Response to Forecast, but subject to Section 3.1(b), Micron will commit to supply quantities sufficient to satisfy the [***] Pre-Qualified Probed Wafer Commitment, [***] Pre-Qualified Probed Wafer Commitment, [***] Base Run at Risk Probed Wafer Commitment, [***] Base Run at Risk Probed Wafer Commitment and Qualified Probed Wafer Commitment, as applicable.


More Definitions of Qualified Probed Wafer

Qualified Probed Wafer means a Probed Wafer with a unique Design ID utilizing a [***] Process Technology Node that is requested to be manufactured by JDP Committee at the Singapore Fab. “[***] Pre-Qualified Probed Wafer Commitment” shall have the meaning set forth in Section 2.1(a)(i). “[***] Pre-Qualified Probed Wafer Demand Forecast” shall have the meaning set forth in Section 3.1(a)(i). “[***] Run at Risk Probed Wafer” means a Probed Wafer to be manufactured utilizing the [***] Process Technology Node that is requested to be started by Intel (but not requested to be started by the JDP Committee), and is started at the Singapore Fab before the [***] Initial Joint Qualification Release. “[***] Run at Risk Probed Wafer Demand Forecast” shall have the meaning set forth in Section 3.1(a)(iii). “[***] Base Run at Risk Probed Wafer Commitment” shall have the meaning set forth in Section 2.1(c).

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