Qualified Probed Wafer definition

Qualified Probed Wafer means a Qualified Probed Wafer with a unique Design ID that is completed at the Singapore Fab after the applicable Initial Joint Qualification Release.
Qualified Probed Wafer means a Probed Wafer with a unique Design ID utilizing a [***] Process Technology Node that is requested to be manufactured by the JDP Committee at the Singapore Fab. “[***] Pre-Qualified Probed Wafer Commitment” shall have the meaning set forth in Section 2.1(a)(ii). “[***] Pre-Qualified Probed Wafer Demand Forecast” shall have the meaning set forth in Section 3.1(a)(ii). “[***] Products” means Pre-Qualified Probed Wafers, Run at Risk Probed Wafers or Qualified Probed Wafers manufactured on the [***] Process Technology Node. “[***] Run at Risk Probed Wafer” means a Probed Wafer to be manufactured utilizing the [***] Process Technology Node that is requested to be started by Intel (but not requested to be started by the JDP Committee), and is started at the Singapore Fab before the [***] Initial Joint Qualification Release. “[***] Run at Risk Probed Wafer Demand Forecast” shall have the meaning set forth in Section 3.1(a)(iv).
Qualified Probed Wafer means a Probed Wafer with a unique Design ID utilizing a [***] Process Technology Node that is requested to be manufactured by JDP Committee at the Singapore Fab. “[***] Pre-Qualified Probed Wafer Commitment” shall have the meaning set forth in Section 2.1(a)(i). “[***] Pre-Qualified Probed Wafer Demand Forecast” shall have the meaning set forth in Section 3.1(a)(i). “[***] Run at Risk Probed Wafer” means a Probed Wafer to be manufactured utilizing the [***] Process Technology Node that is requested to be started by Intel (but not requested to be started by the JDP Committee), and is started at the Singapore Fab before the [***] Initial Joint Qualification Release. “[***] Run at Risk Probed Wafer Demand Forecast” shall have the meaning set forth in Section 3.1(a)(iii). “[***] Supplemental Supply Agreement” means the [***] Supplemental Supply Agreement, dated as of the Effective Date, by and among Intel, MSA and MTI. “[***] Base Run at Risk Probed Wafer Commitment” shall have the meaning set forth in Section 2.1(c). Exhibit A-1 “[***] Design ID Ready Date” means the date that the [***] that the first Design ID with respect to [***] Process Technology Node is ready to commence manufacture at the Singapore Fab. “[***] Incremental Run at Risk Probed Wafer Commitment” shall have the meaning set forth in Section 2.1(c).

Examples of Qualified Probed Wafer in a sentence

  • The Qualified Probed Wafer Demand Forecast will include desired Qualified Probed Wafer breakout by Design ID, Process Technology Node, process revision and probe test revision.

  • In addition, the Qualified Probed Wafer Demand Forecast will include the level of Probe Testing, marking specification and packaging requirements, requested delivery date and place of delivery for the Qualified Probed Wafers, which information will be updated by Intel on a weekly basis as necessary.

  • Intel will base the Qualified Probed Wafer Demand Forecast on Singapore Fab yield forecasts provided by Micron.

  • The Qualified Probed Wafer Demand Forecast will be [***] for the [***] and [***] thereafter.

  • Intel will update the Qualified Probed Wafer Demand Forecast on a weekly or monthly basis, as needed, utilizing the demand planning process in effect between the Parties as of the Effective Date or as may be revised from time to time by mutual agreement of the Parties.

  • If Micron furnishes Intel with a Response to Forecast that commits to supply quantities greater than the Qualified Probed Wafer Commitment in the Ramp Period or an Order Year, but no greater than the applicable Demand Forecast, then the Qualified Probed Wafer Commitment in the Ramp Period or that Order Year shall be deemed to be the greater amounts indicated in the Response to Forecast.

  • Within a commercially reasonable period of time (or within a time period mutually agreed by the Parties from time-to-time) following Micron’s actual, direct receipt of each Qualified Probed Wafer Demand Forecast, Micron shall furnish Intel with a written response indicating what portion of the Qualified Probed Wafer Demand Forecast that Micron will commit to supply (the “Response to Forecast”).

  • The [***] Pre-Qualified Probed Wafer Demand Forecast, [***] Pre-Qualified Probed Wafer Demand Forecast, [***] Run at Risk Probed Wafer Demand Forecast, [***] Run at Risk Probed Wafer Demand Forecast and Qualified Probed Wafer Demand Forecast shall be collectively referred to herein as the “Demand Forecast(s)”.

  • Any such adjustment to Intel’s Qualified Probed Wafer Commitment shall not reduce Micron’s Qualified Probed Wafer Commitment, however, unless waived by Intel.

  • Each Purchase Order shall specify the following items: (a) Purchase Order number; (b) description and part number of each different Qualified Probed Wafer; (c) forecasted quantity of Probed Wafers for each different Design ID; (d) the Estimated Price and total Estimated Price for each different Design ID, and total Estimated Price for all Qualified Probed Wafers ordered; and (e) other terms (if any) that are mutually agreed in writing by the Parties.


More Definitions of Qualified Probed Wafer

Qualified Probed Wafer means a Probed Wafer with a unique Design ID utilizing a [***] Process Technology Node that is requested to be manufactured by JDP Committee at the Singapore Fab. “[***] Pre-Qualified Probed Wafer Commitment” shall have the meaning set forth in Section 2.1(a)(i). “[***] Pre-Qualified Probed Wafer Demand Forecast” shall have the meaning set forth in Section 3.1(a)(i). “[***] Run at Risk Probed Wafer” means a Probed Wafer to be manufactured utilizing the [***] Process Technology Node that is requested to be started by Intel (but not requested to be started by the JDP Committee), and is started at the Singapore Fab before the [***] Initial Joint Qualification Release. “[***] Run at Risk Probed Wafer Demand Forecast” shall have the meaning set forth in Section 3.1(a)(iii). “[***] Base Run at Risk Probed Wafer Commitment” shall have the meaning set forth in Section 2.1(c).

Related to Qualified Probed Wafer

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