Wafer Outs definition

Wafer Outs means completed Wafers processed for delivery to AMD.
Wafer Outs means finished wafers. Such Annual Quantity Projections shall be a good faith estimate by TI but shall be for informational purposes only and not constitute a binding purchase obligation of TI. The Annual Quantity Projections may be issued electronically.

Examples of Wafer Outs in a sentence

  • With respect to [****] Wafer Outs containing [****]nm MPU Products that were originally ordered by AMD for delivery in [****], [****], such [****] have been or will be invoiced at prices calculated according to Section 7.1(a) and Exhibit A of the Agreement, and the prices for [****] will not be modified by Schedule D of this Amendment.

  • For purposes of this Agreement, "Wafer Outs" means finished wafers.

  • The term “NPI Wafers” shall mean Wafer Outs of Product Development Wafers processed during the 2014 Period that are tied to a new Product introduction and are not Production Wafers or multi-project wafers.

  • By the 15th of May of each year during the Term, TI shall provide to Amkor the annual quantities of Wafer Outs by technology node (e.g., C10, C07, non-copper C05) estimated to be purchased from Amkor by TI for the upcoming three (3) to five (5) year time period (the "Annual Quantity Projections").

  • By the 15th of May of each year during the Term, TI shall provide to Amkor the annual quantities of Wafer Outs by technology node (e.g., C10, C07) estimated to be purchased from Amkor by TI for the upcoming three (3) to five (5) year time period (the "Annual Quantity Projections").

  • On the fifteenth (15th) day of each month (or on the last preceding Business Day prior to the fifteenth (15th) day if the fifteenth (15th) day is on a weekend or holiday) following the first Product Qualification, Sipex shall provide Silan with a non-binding, six (6) month rolling forecast (the "Forecast") of the monthly quantity of wafer starts and Wafer Outs, by Sipex Product (that have achieved Product Qualification), anticipated to be ordered by Sipex from Silan.

  • Figure 1: Influence on Cycle Time, WIP, and Wafer Outs After the surge impulse is initiated, a linear increase in WIP can be observed.

  • TSMC and QuickLogic will enter into a rolling "Take or Pay" contract, for a period of three (3) years, starting on the date of first Risk Production Wafer Outs and incrementing annually by mutual consent, of substantially the same from as the "Take or Pay" contracts currently offered to TSMC's existing customers.

Related to Wafer Outs

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