Automatic Vectorization. Fine-grain data level parallelism is one of the most effective ways to achieve scalable per- formance of numerical computations. It is pervasive in graphical accelerators. Automatic vectorization for modern short-SIMD instructions has been a popular topic, with target-specific as well as retargetable compilers for the ARM Neon, Intel AVX an SSE, IBM Altivec and Cell SPU; all of these works had a successful impact on production compilers [47, 9, 31, 32]. Exploiting subword parallelism in modern SIMD architectures, however, suffers from several limitations and overheads (involving alignment, redundant loads and stores, support for reduc- tions and more) which complicate the optimization dramatically. Automatic vectorization was also extended to handle more sophisticated control-flow restructuring including if-conversion [41] and outer-loop vectorization [32]. Classical techniques of loop distribution and loop interchange [46, 2, 42] can dramatically impact the profitability of vectorization. Leading optimizing compilers recognize the importance of devising a cost model for vector- ization, but have so far provided only partial solutions. Wu et al. conclude [47] regarding the XL compiler that: “Many further issues need to be investigated before we can enjoy the performance benefit of simdization for a wide range of applications. The more important features among them are more advanced handling of non stride-one accesses and the ability to decide when simdization is profitable. Equally important is a better understanding of the interaction between simdization and other optimizations in a compiler framework.”3 Likewise, Bik stresses the importance of user hints in Intel’s ICC vectorizer profitability estima- tion [9], to avoid vectorization slowdowns due to: “the performance penalties of data rearrangement instructions, misaligned memory references, failure of store-to-load forwarding, or additional overhead of run-time optimizations to enable vectorization.” On the other hand opportunities may be missed due to overly conservative heuristics. These state-of-the-art vectorizing compilers incorporate a cost model to decide whether vectorization is expected to be profitable. These models however typically apply to a single loop or basic-block, and do not consider alternatives combined with other transformations at the loop-nest level. Loop-nest auto-vectorization in conjunction with loop-interchange has been addressed in prior work [1, 46, 2]. However, this was ty...
