Control 1 Pin Sample Clauses

Control 1 Pin. ‌ Programmable Control 1 Pin is an input pin from the Host, operating with programmable logic. This pin is pulled up in the CFP4 module. It can be re-programmed over MDIO registers to another MDIO control register while the module is in any steady state except Reset. The CFP MSA specifies that the default function be TX Disable (TX_DIS) with active-high logic. If the other function besides TX_DIS is configured for this pin, there is no way to assert TX disable via a hardware pin.
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Control 1 Pin. Programmable Control Pin 1 (PRG_CNTL1) is an input pin from the Host, operating with programmable logic. It is pulled up in the CFP module. It can be re-programmed over MDIO registers to another MDIO control register while the module is in any steady state except Reset. The CFP MSA specifies that the default function be Transmit & Receive circuitry reset (TRXIC_RSTn) with active-low logic. When TRXIC_RSTn is asserted (driven low) the digital transmit and receive circuitry is reset clearing all FIFOs and/or resetting all CDRs and/or DLLs. When de-asserted, the digital transmit and receive circuitry resumes normal operation.
Sample 1

Related to Control 1 Pin

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