Common use of Hardware Control Pins Clause in Contracts

Hardware Control Pins. The CFP8 Module supports real-time control functions via hardware pins, listed in Table 2-1. Specifications of the CFP8 hardware control pins are given in Ref. [1], with the changes listed below. Pin # Symbol Description I/O Logic “H” “L” Pull-up /down 96 TX_DIS (PRG_CNTL1) Transmitter Disable (Optionally configurable as Programmable Control after Reset1) I 3.3V LVCMOS Disable2 Enable2 Pull – Up3 94 MOD_LOPWR Module Low Power Mode I 3.3V LVCMOS Low Power Enable Pull – Up3 88 MOD_RSTn Module Reset, Active Low (invert) I 3.3V LVCMOS Enable Reset Pull – Down4 1 When Programmable Control is configured, MSA Default is TX_DIS. 2 Per CFP MSA Management Interface Specification [4] when PRG_CNTL1 is configured for this pin.

Hardware Control Pins. The CFP8 Module supports real-time control functions via hardware pins, listed in Table 2-1. Specifications of the CFP8 hardware control pins are given in Ref. [1], with the changes listed below. Pin # Symbol Description I/O Logic “H” “L” ³H´ ³L´ Pull-up /down 96 TX_DIS (PRG_CNTL1) Transmitter Disable (Optionally configurable as Programmable Control after Reset1) I 3.3V LVCMOS Disable2 Enable2 Pull – Up3 ±Up3 94 MOD_LOPWR Module Low Power Mode I 3.3V LVCMOS Low Power Enable Pull – Up3 ±Up3 88 MOD_RSTn Module Reset, Active Low (invert) I 3.3V LVCMOS Enable Reset Pull – ± Down4 1 When Programmable Control is configured, MSA Default is TX_DIS. 2 Per CFP MSA Management Interface Specification [4] when PRG_CNTL1 is configured for this pin.

Hardware Control Pins. The CFP8 CFP4 Module supports real-time control functions via hardware pins, listed in Table 21-1. Specifications of the CFP8 CFP4 hardware control pins are given in Ref. [1Ref.[1], with the following changes listed below. Table 1-1: Control Pins‌ Pin # Symbol Description I/O Logic “H” “L” Pull-up /down 96 11 TX_DIS (PRG_CNTL1PRG_CNTL) Transmitter Disable (Optionally configurable as Programmable Control after Reset1) I 3.3V LVCMOS Disable2 Enable2 Pull – Up3 94 14 MOD_LOPWR Module Low Power Mode I 3.3V LVCMOS Low Power Enable Pull – Up3 88 16 MOD_RSTn Module Reset, Active Low (invert) I 3.3V LVCMOS Enable Reset Pull – Down4 1 When Programmable Control is configured, MSA Default is TX_DIS. 2 Per CFP MSA Management Interface Specification [4] when PRG_CNTL1 is configured for this pin.Down4

Hardware Control Pins. ‌ The CFP8 CFP4 Module supports real-time control functions via hardware pins, listed in Table 21-1. Specifications of the CFP8 CFP4 hardware control pins are given in Ref. [1Ref.[1], with the following changes listed below. Table 1-1: Control Pins‌ Pin # Symbol Description I/O Logic “H” “L” Pull-up /down 96 11 TX_DIS (PRG_CNTL1PRG_CNTL) Transmitter Disable (Optionally configurable as Programmable Control after Reset1) I 3.3V LVCMOS Disable2 Enable2 Pull – Up3 94 14 MOD_LOPWR Module Low Power Mode I 3.3V LVCMOS Low Power Enable Pull – Up3 88 16 MOD_RSTn Module Reset, Active Low (invert) I 3.3V LVCMOS Enable Reset Pull – Down4 1 When Programmable Control is configured, MSA Default is TX_DISTXDIS. 2 Per CFP MSA Management Interface Specification [43] when PRG_CNTL1 PRG_CNTL is configured for this pin.

Hardware Control Pins. The CFP8 CFP4 Module supports real-time control functions via hardware pins, listed in Table 21-1. Specifications of the CFP8 CFP4 hardware control pins are given in Ref. [1Ref.[1], with the following changes listed below. Pin # Symbol Description I/O Logic “H” “L” Pull-up /down 96 11 TX_DIS (PRG_CNTL1PRG_CNTL) Transmitter Disable (Optionally configurable as Programmable Control after Reset1) I 3.3V LVCMOS Disable2 Enable2 Pull – Up3 94 14 MOD_LOPWR Module Low Power Mode I 3.3V LVCMOS Low Power Enable Pull – Up3 88 16 MOD_RSTn Module Reset, Active Low (invert) I 3.3V LVCMOS Enable Reset Pull – Down4 1 When Programmable Control is configured, MSA Default is TX_DISTXDIS. 2 Per CFP MSA Management Interface Specification [43] when PRG_CNTL1 PRG_CNTL is configured for this pin.