Hardware Interlock. The CFP2 module Hardware Interlock function is specified in Ref. [1] with power classes defined in the below Table 2-2. Hardware Interlock Description Power Class CFP2 Module Power Dissipation W MSB LSB
1 1 > 4 > 9
Hardware Interlock. Not supported in CFP8 module
Hardware Interlock. The CFP MSA encompasses a wide range of applications and thus the expected power consumption of the CFP module will vary accordingly. Often systems are limited in the amount of power which can be dissipated in various module slots. The Hardware Interlock provides for four different power consumption levels. The module shall compare the maximum power dissipation under vendor specified operating conditions to the host system cooling capacity value communicated via the Hardware Interlock. See the Table 2-2: Hardware Interlock for definition of the Hardware Interlock function. The Hardware Interlock pins shall be kept at a static value during the transient Initialize state, and any change to the values will result in unpredictable module behavior.
Hardware Interlock. The CFP MSA encompasses a wide range of applications and thus the expected power consumption of the CFP module will vary accordingly. Often systems are limited in the amount of power which can be dissipated in various module slots. The Hardware Interlock provides for four different power consumption levels. The module shall compare the maximum power dissipation under vendor specified operating conditions to the host system cooling capacity value communicated via the Hardware Interlock. See the Table 2-2: Hardware Interlock for definition of the Hardware Interlock function.
