Receiver Monitor Clock (Option). The CFP2 module may optionally supply a receiver monitor clock for M x 25 Gbit/s applications. This option is not available for M x 10 Gbit/s applications. The receiver monitor clock is intended to be used as a reference for measurements of the optical input. If provided, the clock shall operate at a rate relative to the optical network lane rate of 1/8 or 1/32 of 25 Gbit/s for 100 Gbit/s (4x25 Gbit/s, 8x25 Gbit/s) applications. Another option is a clock at 1/40 or 1/160 the rate of (host) transmitter electrical input data for M x 25 Gbit/s. Clock termination is shown in Figure 4-1. Detailed clock characteristics are specified in Table 4-3. 6 The spectrum of the jitter within this frequency band is undefined. The CFP2 shall meet performance requirements with worst case condition of a single jitter tone of 10ps RMS at any frequency between 10 KHz and 10 MHz. 7 For Telecom applications better frequency may be required. Impedance Zd 80 100 120 Ω Frequency See Table 4-4: CFP2 Module Clocking Signals Output Differential Voltage VDIFF 400 1200 mV Peak to Peak Differential Clock Duty Cycle 40 60 % Datacom 100GBASE-SR4/LR4/ER4 Telecom OTU4 REFCLK Optional I 1/160 (161.1328 MHz) or 1/40 (644.5313 MHz) 1/160 (174.7031 MHz) 1/8 (3.22266 GHz) 1/8 (3.49406 GHz) or or TX_MCLK 1/32 (805.665 MHz) 1/32 (873.515 MHz) Optional O or or RX_MCLK 1/40 (644.5313 MHz) 1/40 (698.8123 MHz) or or 1/160 (161.1328 MHz) 1/160 (174.7031 MHz) M x 10 Gbit/s Default Host Lane Rate Datacom Datacom Clock Name Status I/O 100GBASE-LR4 100GBASE-SR10 40GBASE-FR Telecom Optional rate 40GBASE-SR4/LR4/ER4 OTU4 10x10GBASE-SR/LR OC-768/STM-256,OTU3 REFCLK Optional I 1/64 of host lane rate (161.1328 MHz) 1/64 of host lane rate (D : 161.1328 MHz) (T : 1xx MHz) 1/16 of host lane rate (D : 644.5313 MHz) (T : 6xx MHz) Note: Multi-protocol modules are recommended to adopt the clock rate used in Telecom applications.
Receiver Monitor Clock (Option). The CFP module may supply an optional receiver monitor clock. This clock is intended to be used as a reference for measurements of the optical input. If provided, the clock shall operate at a rate relative to the 10 The spectrum of the jitter within this frequency band is undefined. The CFP shall meet performance requirements with worst case condition of a single jitter tone of 10ps RMS at any frequency between 10KHz and 10MHz 11 For Telecom applications better frequency may be required. optical lane rate of 1/16 rate for 40Gbit/s applications and 1/8 rate of 25Gbit/s for 100Gbit/s applications. Another option is a clock at 1/16 or 1/64 rate of the receiver electrical output data. Clock termination is shown in Figure 4-1. Detailed clock characteristics are specified in Table 4-3. Impedance Zd 80 100 120 Ω Frequency See Table 4-4: CFP Module Clocking Signals Output Differential Voltage VDIFF 400 1200 mV Peak to Peak Differential Clock Duty Cycle 40 60 % M ≠ N Datacom 100GBASE-LR4 100GBASE-ER4 40GBASE-FR12,13 M = N 100GBASE-SR10 40GBASE-SR4 40GBASE-LR4 M ≠ N Telecom OC-768, OTN (40G,43G) REFCLK Required I 1/64 of host lane rate 1/64 of host lane rate 1/64 of host lane rate 1/16 of host lane rate TX_MCLK Optional O 1/8 of network lane rate 1/16 of network lane rate 1/16 of network lane rate 1/16, 1/64 of host lane rate RX_MCLK Optional O 1/8 of network lane rate 1/16 of network lane rate 1/16 of network lane rate 1/16, 1/64 of host lane rate Also, 1/16 of optical lane rate clock is recommended for TX_MCLK and RX_MCLK. 13 Multi-protocol modules are recommended to adopt the clock rate used in Telecom applications. Figure 4-4: Example of clocking for M≠N applications14 14 Use of oscillator for receiver reference clock is application dependent
Receiver Monitor Clock (Option). The CFP2 module may optionally supply a receiver monitor clock for M x 25 Gbit/s applications. This option is not available for M x 10 Gbit/s applications. The receiver monitor clock is intended to be used as a reference for measurements of the optical input. If provided, the clock shall operate at a rate relative to the optical network lane rate of 1/8 or 1/32 of 25 Gbit/s for 100 Gbit/s (4x25 Gbit/s, 8x25 Gbit/s) applications.
Receiver Monitor Clock (Option). The CFP module may supply an optional receiver monitor clock. This clock is intended to be used as a reference for measurements of the optical input. If provided, the clock shall operate at a rate relative to the optical lane rate of 1/16 rate for 40Gbit/s applications and 1/8 rate of 25Gbit/s for 100Gbit/s applications. Another option is a clock at 1/16 or 1/64 rate of the receiver electrical output data. REFCLK Required I 1/64 of electrical lane rate 1/64 of electrical lane rate 1/64 of electrical lane rate 1/16 of electrical lane rate TX_MCLK Optional O 1/8 of optical lane rate 1/16 of optical lane rate 1/16 of optical rate 1/16, 1/64 of electrical lane rate RX_MCLK Optional O 1/8 of optical lane rate 1/16 of optical lane rate 1/16 of optical rate 1/16, 1/64 of electrical lane rate ` 7 Detailed reference clock characteristics are under study. 8 The term “40GBASE-LR” implies a 40GbE serial optical interface. x M CFP module Controller x N RX Optical Optics DMUX Interface IC(s) x N TX Optical Optics MUX x M Control/ Alarm CDR (optional) CDR CDR RXDATA REFCLK CDR (optional)
