Semantics of VDM-RT Sample Clauses

Semantics of VDM-RT. ‌ The semantics of VDM-RT adopted by the Overture C code generator is fully documented in INTO-CPS deliverables D2.1b [FCL+15] and D2.2b [FCC+16]. The semantic work is rooted in Hoare and He’s Unifying Theories of Programming (UTP) [HJ98]. Here we give a brief overview of the most important aspects of the semantics. Features of VDM-SL The expression language of VDM-RT forms the basic mathematical core of the language. The mathematical vocabulary is standard and ranges over basic number domains, the Boolean domain, sets, sequences, maps etc. Expressions can refer to state variables, but they do not admit non-deterministic constructs, such as underspecified choice between values (e.g. VDM-RT’s let-be-such-that construct.) Therefore, expression evaluation is deterministic modulo specification state, that is, an expression evaluated in the context of an instance of a class will always be deterministic relative to that object’s state. The semantics of the expression language of VDM-RT is therefore assumed to be the standard mathematical one, and a direct semantic mapping into UTP expressions is assumed. Features of VDM++ The feature of VDM++ of primary interest to code generation is object orientation. The semantics defines nine fundamental conditions governing the structure of a valid object-oriented specification in VDM++. Later, we show that the code emitted by the Overture C code generator is in conformance with these conditions, with a few justifiable exceptions. In brief, the conditions are:
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