Common use of TABLE LIST Clause in Contracts

TABLE LIST. Table 2-1: Hardware Control Pins 12 Table 2-2: Hardware Alarm Pins 14 Table 2-3: Management Interface Pins (MDIO) 15 Table 2-4: Optional MOD_SELn Timing Parameters 18 Table 4-1: Voltage Power Supply 22 Table 4-2: Optional Reference Clock Characteristics 26 Table 4-3: Optional Monitor Clock Characteristics 27 Table 4-4: CFP8 Module Clocking Signals 28 Table 5-1: CFP8 Mechanical Characteristics 36 Table 5-2: CFP8 Module Insertion, Extraction Forces 37 Table 5-3: Optical Connectors 39 Table 5-4: CFP8 Host Connector Assembly 40 Table 5-5: CFP8 Pin Map 42 Table 5-6: CFP8 Top Row Pin Descriptions 43 Table 5-7: CFP8 Bottom Row Pin Descriptions 45 Table 5-8: CFP8 Bail Latch Color Coding 48 Figure 1-1: CFP8 Functional Block Diagram 11 Figure 2-1: Reference +3.3V LVCMOS Output Termination 16 Figure 2-2: Reference 3.3V LVCMOS Input Termination 17 Figure 2-3: Reference MDIO Interface Termination 17 Figure 2-4: Optional MOD_SELn Timing Diagram 18 Figure 3-1 PHYADR Setup Sequence for Optional Shared MDIO bus 20 Figure 4-1: High Speed I/O for Data and Clocks 23 Figure 4-2: CFP8 Module Optional Loopback Orientation 25 Figure 4-3: Example of Clocking for 16 x 25 Gb/s CFP8 Applications 29 Figure 4-4:Example of Clocking for 8 x 50 Gb/s XXX-4 CFP8 Applications 29 Figure 5-1: CFP8 Module & CFP8 Module Mated in Single and Dual Port Systems 30 Figure 5-2: Host Cage System and Mounting Method Overview 31 Figure 5-3: CFP8 Module Plug Connector Assembly 32 Figure 5-4: CFP8 Single & Double Port Host Connector Cover Assemblies 33 Figure 5-5: CFP8 Host Connector Assembly 33 Figure 5-6: CFP8 Pin Map Connector Engagement 34 Figure 5-7: CFP8 Module Dimension Overview 35 Figure 5-8: Riding Heat Sink 38 Figure 5-9: Host Cage Top Surface Opening 39 Figure 5-10: CFP8 Optical Connector Position 40 Figure 5-11: CFP8 Connector Pin Map Orientation 41 Figure 5-12 CFP8 Pin Map for Multiple Configurations 47 Figure 5-13: CFP8 Module Label Recess 48 [1] CFP MSA Hardware Specification, Revision 1.4, June 7, 2010. xxxx://xxx.xxx- xxx.xxx/Xxxxxxxxx/XXX-XXX-XX-Xxxx-xxx0-00.xxx [2] CFP MSA CFP2 Hardware Specification, Revision 1.0, July 31, 2013. xxxx://xxx.xxx- xxx.xxx/Xxxxxxxxx/XXX0_XX-Xxxx-xxx0.0.xxx [3] CFP MSA CFP4 Hardware Specification, Revision 1.1, March 18, 2015. xxxx://xxx.xxx- xxx.xxx/Xxxxxxxxx/XXX-XXX_XXX0_XX-Xxxx-xxx0.0.xxx [4] CFP MSA Management Interface Specification, Version 2.4, June 8, 2015. xxxx://xxx.xxx- xxx.xxx/Xxxxxxxxx/XXX_XXX_XXX_X0x0x00x.xxx (to be updated) [5] IEEE P802.3bs, 400 Gb/s Ethernet Task Force, xxxx://xxxx000.xxx/3/bs/index.html [6] IEEE Std. 802.3TM-2015, Annexes 83A, 83B, 83E, 86A. [7] IEEE Std. 802.3TM-2015, Cl. 45, Management Data Input/Output (MDIO) Interface. xxxx://xxxxxxxxx.xxxx.xxx/about/get/802/802.3.html [8] ITU-T Recommendation X.709 (2012) Interfaces for the Optical Transport Network (OTN). xxxx://xxx.xxx.xxx/rec/T-REC-G/en [9] ITU-T Recommendation X.707 (2007) Network node interface for the synchronous digital hierarchy (SDH). xxxx://xxx.xxx.xxx/rec/T-REC-G/en [10] OIF-CEI-3.1,Common Electrical I/O (CEI) – Electrical and Jitter Interoperability Agreements for 6G+ bps, 11G+ bps and 25G+ bps I/O, February 18, 2014. xxxx://xxx.xxxxxxx.xxx/public/documents/OIF_CEI_03.1.pdf [11] SNIA SFF TA TWG INF-8077i 10 Gigabit Small Form Factor Pluggable Module. xxxx://xxx.xxxx.xxx/sff/specifications [12] SNIA SFF TA TWG SFF-8431 SFP+ 10 Gb/s and Low Speed Electrical Interface. xxxx://xxx.xxxx.xxx/sff/specifications

TABLE LIST. Table 21-1: Hardware Control Pins 12 9 Table 21-2: Hardware Alarm Pins 14 10 Table 21-3: Management Interface Pins (MDIO) 15 Table 2-4: Optional MOD_SELn Timing Parameters 18 11 Table 4-1: Voltage Power Supply 22 16 Table 4-2: Optional Reference Clock Characteristics 26 19 Table 4-3: Optional Monitor Clock Characteristics 27 20 Table 4-4: CFP8 CFP4 Module Clocking Signals 28 20 Table 5-1: CFP8 CFP4 Mechanical Characteristics 36 26 Table 5-2: CFP8 CFP4 Module Insertion, Extraction Forces 37 26 Table 5-3: Optical Connectors 39 28 Table 5-4: CFP8 CFP4 Host Connector Assembly 40 29 Table 5-5: CFP8 CFP4 4x25Gbpt/s Pin Map 42 31 Table 5-6: CFP8 Top CFP4 Bottom Row Pin Descriptions 43 Piin Description for 4x25 Gbit/s Applications 32 Table 5-7: CFP8 Bottom Row Pin Descriptions 45 Table 5-8: CFP8 CFP4 Bail Latch Color Coding 48 33 Figure 1-1: CFP8 CFP4 Functional Block Diagram 11 8 Figure 2-1: Reference +3.3V LVCMOS Output Termination 16 12 Figure 2-2: Reference 3.3V LVCMOS Input Termination 17 13 Figure 2-3: Reference MDIO Interface Termination 17 Figure 2-4: Optional MOD_SELn Timing Diagram 18 Figure 3-1 PHYADR Setup Sequence for Optional Shared MDIO bus 20 14 Figure 4-1: High Speed I/O for Data and Clocks 23 16 Figure 4-2: CFP8 CFP4 Module Optional Loopback Orientation 25 17 Figure 4-3: Example of Clocking for 16 4 x 25 GbGbit/s CFP8 CFP4 Applications 29 21 Figure 4-4:: Example of Clocking for 8 4 x 50 Gb10 Gbit/s XXX-4 CFP8 CFP4 Applications 29 21 Figure 5-1: CFP8 CFP4 Module & CFP8 CFP4 Module Mated in Single and Dual Host Quad Port Systems 30 System 22 Figure 5-2: Host Cage System and Mounting Method Overview 31 22 Figure 5-3: CFP8 CFP4 Module Plug Connector Assembly 32 23 Figure 5-4: CFP8 Single & Double CFP4 Quad Port Host Connector Cover Assemblies 33 Assembly 23 Figure 5-5: CFP8 CFP4 Host Connector Assembly 33 24 Figure 5-6: CFP8 CFP4 Pin Map Connector Engagement 34 24 Figure 5-7: CFP8 CFP4 Module Dimension Overview 35 25 Figure 5-8: Riding Heat Sink 38 27 Figure 5-9: Host Cage Top Surface Opening 39 27 Figure 5-10: CFP8 Optical CFP4 Connector Position 40 Pin Map Orientation 30 Figure 5-11: CFP8 Connector Pin Map Orientation 41 Figure 5-12 CFP8 Pin Map for Multiple Configurations 47 Figure 5-13: CFP8 CFP4 Module Label Recess 48 33 [1] CFP MSA Hardware Specification, Revision 1.4, June 7, 2010. xxxx://xxx.xxx- xxx.xxx/Xxxxxxxxx/XXX-XXX-XX-Xxxx-xxx0-00.xxx [2] CFP MSA CFP2 Hardware Specification, Revision 1.0, July 31, 2013. xxxx://xxx.xxx- xxx.xxx/Xxxxxxxxx/XXX0_XX-Xxxx-xxx0.0.xxx [3] CFP MSA CFP4 Hardware Specification, Revision 1.1, March 18, 2015. xxxx://xxx.xxx- xxx.xxx/Xxxxxxxxx/XXX-XXX_XXX0_XX-Xxxx-xxx0.0.xxx [4] CFP MSA Management Interface Specification, Version 2.4, June 8March, 2015. xxxx://xxx.xxx- xxx.xxx/Xxxxxxxxx/XXX_XXX_XXX_X0x0x00x.xxx (to be updated) [4] IEEE P802.3bm, 40Gbit/s and 100Gbit/s Operation Over Fiber Optic Cables Task Force, [5] IEEE P802.3bs, 400 Gb/s Ethernet Task Force, xxxx://xxxx000.xxx/3/bs/index.html [6] IEEE Std. 802.3TM-2015Std 802.3TM-2012, Annexes 83A, 83B, 83E, and 86A. [76] IEEE Std. 802.3TM-2015Std 802.3TM-2012, Cl. 45, Management Data Input/Output (MDIO) Interface. xxxx://xxxxxxxxx.xxxx.xxx/about/get/802/802.3.html [87] ITU-T Recommendation X.709 G.709 (2012) Interfaces for the Optical Transport Network (OTN). xxxx://xxx.xxx.xxx/rec/T-REC-G/en [98] ITU-T Recommendation X.707 G.707 (2007) Network node interface for the synchronous digital hierarchy (SDH). xxxx://xxx.xxx.xxx/rec/T-REC-G/en [9] OIF-CEI-3.0, xxxx://xxx.xxxxxxx.xxx/public/documents/OIF_CEI_03.0.pdf [10] OIF-CEI-3.1,Common Electrical I/O (CEI) – Electrical and Jitter Interoperability Agreements for 6G+ bps, 11G+ bps and 25G+ bps I/O, February 18, 2014. xxxx://xxx.xxxxxxx.xxx/public/documents/OIF_CEI_03.1.pdf [11] SNIA SFF TA TWG Committee INF-8077i 10 Gigabit Small Form Factor Pluggable Module. xxxx://xxx.xxxx.xxx/sff/specifications Module [1211] SNIA SFF TA TWG Committee SFF-8431 Specifications for Enhanced Small Form Factor Pluggable Module SFP+ 10 Gb/s and Low Speed Electrical Interface. xxxx://xxx.xxxx.xxx/sff/specifications1 GENERAL‌

TABLE LIST. Table 2-1: Hardware Control Pins 12 Table 2-2: Hardware Alarm Pins 14 Table 2-3: Management Interface Pins (MDIO) 15 Table 2-4: Optional MOD_SELn Timing Parameters 18 Table 4-1: Voltage Power Supply 22 Table 4-2: Optional Reference Clock Characteristics 26 Table 4-3: Optional Monitor Clock Characteristics 27 Table 4-4: CFP8 Module Clocking Signals 28 Table 5-1: CFP8 Mechanical Characteristics 36 Table 5-2: CFP8 Module Insertion, Extraction Forces 37 Table 5-3: Optical Connectors 39 Table 5-4: CFP8 Host Connector Assembly 40 Table 5-5: CFP8 Pin Map 42 Table 5-6: CFP8 Top Row Pin Descriptions 43 Table 5-7: CFP8 Bottom Row Pin Descriptions 45 Table 5-8: CFP8 Bail Latch Color Coding 48 Figure 1-1: CFP8 Functional Block Diagram 11 Figure 2-1: Reference +3.3V LVCMOS Output Termination 16 Figure 2-2: Reference 3.3V LVCMOS Input Termination 17 Figure 2-3: Reference MDIO Interface Termination 17 Figure 2-4: Optional MOD_SELn Timing Diagram 18 Figure 3-1 PHYADR Setup Sequence for Optional Shared MDIO bus 20 Figure 4-1: High Speed I/O for Data and Clocks 23 Figure 4-2: CFP8 Module Optional Loopback Orientation 25 Figure 4-3: Example of Clocking for 16 x 25 Gb/s CFP8 Applications 29 Figure 4-4:Example of Clocking for 8 x 50 Gb/s XXX-4 CFP8 Applications 29 Figure 5-1: CFP8 Module & CFP8 Module Mated in Single and Dual Port Systems 30 Figure 5-2: Host Cage System and Mounting Method Overview 31 Figure 5-3: CFP8 Module Plug Connector Assembly 32 Figure 5-4: CFP8 Single & Double Port Host Connector Cover Assemblies 33 Figure 5-5: CFP8 Host Connector Assembly 33 Figure 5-6: CFP8 Pin Map Connector Engagement 34 Figure 5-7: CFP8 Module Dimension Overview 35 Figure 5-8: Riding Heat Sink 38 Figure 5-9: Host Cage Top Surface Opening 39 Figure 5-10: CFP8 Optical Connector Position 40 Figure 5-11: CFP8 Connector Pin Map Orientation 41 Figure 5-12 CFP8 Pin Map for Multiple Configurations 47 Figure 5-13: CFP8 Module Label Recess 48 [1] CFP MSA Hardware Specification, Revision 1.4, June 7, 2010. xxxx://xxx.xxx- xxx.xxx/Xxxxxxxxx/XXX-XXX-XX-Xxxx-xxx0-00.xxx [2] CFP MSA CFP2 Hardware Specification, Revision 1.0, July 31, 2013. xxxx://xxx.xxx- xxx.xxx/Xxxxxxxxx/XXX0_XX-Xxxx-xxx0.0.xxx [3] CFP MSA CFP4 Hardware Specification, Revision 1.1, March 18, 2015. xxxx://xxx.xxx- xxx.xxx/Xxxxxxxxx/XXX-XXX_XXX0_XX-Xxxx-xxx0.0.xxx [4] CFP MSA Management Interface Specification, Version 2.4, June 8, 2015. xxxx://xxx.xxx- xxx.xxx/Xxxxxxxxx/XXX_XXX_XXX_X0x0x00x.xxx (to be updated) [5] IEEE P802.3bs, 400 Gb/s Ethernet Task Force, xxxx://xxxx000.xxx/3/bs/index.html [6] IEEE Std. 802.3TM-2015, Annexes 83A, 83B, 83E, 86A. [7] IEEE Std. 802.3TM-2015, Cl. 45, Management Data Input/Output (MDIO) Interface. xxxx://xxxxxxxxx.xxxx.xxx/about/get/802/802.3.html [8] ITU-T Recommendation X.709 G.709 (2012) Interfaces for the Optical Transport Network (OTN). xxxx://xxx.xxx.xxx/rec/T-REC-G/en [9] ITU-T Recommendation X.707 G.707 (2007) Network node interface for the synchronous digital hierarchy (SDH). xxxx://xxx.xxx.xxx/rec/T-REC-G/en [10] OIF-CEI-3.1,Common Electrical I/O (CEI) – Electrical and Jitter Interoperability Agreements for 6G+ bps, 11G+ bps and 25G+ bps I/O, February 18, 2014. xxxx://xxx.xxxxxxx.xxx/public/documents/OIF_CEI_03.1.pdf [11] SNIA SFF TA TWG INF-8077i 10 Gigabit Small Form Factor Pluggable Module. xxxx://xxx.xxxx.xxx/sff/specifications [12] SNIA SFF TA TWG SFF-8431 SFP+ 10 Gb/s and Low Speed Electrical Interface. xxxx://xxx.xxxx.xxx/sff/specifications