VDM-RT Interlocking Model Sample Clauses

VDM-RT Interlocking Model. The VDM-RT interlocking controller is in essence a finite automaton whose state is determined by the configuration of five relays R1-R5, each corresponding to a particular route being enabled. To capture the core algorithmic behaviour of the interlocking, we introduce a variable Relay to record the state of relay switches as a boolean vector. The interlocking software controller is then modelled by virtue of a cyclic ex- ecutive that periodically performs the following four sequential tasks:
Sample 1
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VDM-RT Interlocking Model. The VDM-RT interlocking controller is in essence a finite automaton whose state is determined by the configuration of five relays R1-R5, each corre- sponding to a particular route being activated (locked). A fundamental safety property is that two different routes can only be activated simultaneously if their paths do not intersect. Moreover, signals and point switches have to be set consistently with the activated routes at any given time. To capture the core algorithmic behaviour of the interlocking system, we in- troduce a variable Relay to record the state of relay switches as a boolean vec- tor. The interlocking software controller is then modelled by virtue of a cyclic executive that periodically performs the following sequential tasks:
Sample 1

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