BIST-enhanced switch architecture. The switch architecture enriched with the BIST infrastructure is illustrated in Fig.6. Only one section is reported. The figure is necessarily at a high abstraction level, and signal-level connection details previously illustrated in sections 2.3.1 and 2.3.3 are purposely omitted. A test wrapper consisting of multiplexers can be clearly seen, which enables test pattern injec- tion of TPGs in the modules they test. At the output of the input buffer, test patterns are directly fed to the LBDR module, since they are carried by the communication channel as normal network traffic. A multiplexer in front of each output buffer selects between the switch datapath, the test patterns from the LBDR TPG (feeding the LBDR module of the downstream switch), the channel TPG (directly feeding the channel) and the arbiter test responses (checked in the downstream switch). A BIST engine drives the 4 phases of the testing procedure by acting upon the control signals of the test wrapper. During the first three phases (communication channel, crossbar, arbiter testing), outputs of the input buffers are selected to feed the comparator tree, while in the last phase (LBDR testing), all LBDR outputs are selected. Test response check and diagnosis are performed at each clock cycle, and result in the setting of 10 bits, indicating whether each input/output port is faulty or not.
BIST-enhanced switch architecture. The switch architecture enriched with the BIST infrastructure is illustrated in Fig.18(d). A test wrapper consisting of multiplexers can be clearly seen, which enables test pattern injection of the LFSR in the modules it tests. A unique 34 bits LFSR generates the pseudo-random patterns to test in parallel every switch port. Moreover a dedicated 11 bits MISR for every port collects the test response from the output port arbiters and a 38 bits MISR for every port performs the signature analysis of the test responses from the crossbar, the channel and the LBDR blocks. Test diagnosis results in the setting of 10 bits (one for every MISR), indicating whether each input/output port is faulty or not. This meets the requirements of the LBDR configuration algo- rithm in [25]. Interestingly, the testing framework is able to reveal the correct position of multiple faulty channels since a MISR is dedicated to each port. Obviously, it is not possible to distinguish the elementary faulty module inside the faulty port. However, the proposed testing framework is based on the assumption that the functionally coupled modules for an input port are its routing block, its upstream communication channel, the port arbiter and the crossbar multiplexer in the upstream switch associated with that channel. Thus, when one of the above mentioned functionally coupled modules fails then the associated safe logic would be unusable anyway.
