Error Protection Techniques Sample Clauses

Error Protection Techniques. As it has been already mentioned, a set of different error protection techniques is implemented on the DRM to provide fault-tolerant features. These techniques can be classified in two general types: those techniques oriented to mitigate or restrict the effect of potential errors and those ones which enable it to detect and correct them. Regarding the first type, two techniques are considered: Mitigation technique #1: Xilinx Isolation Design Flow Xilinx Isolation Design Flow (IDF) is a design technique defined by the FPGA manufacturer Xilinx [4], which allows for fault-containment at a FPGA module level. It makes use of the standard Xilinx design tools and requires attention to the design layout by respecting strict set of rules. The objective of this technique is to isolate the impact of single failures to a specific module reducing drastically their effect on the system. IDF consists of first partitioning the design in different hierarchical modules and afterwards add the design layout and routing constraints so that each partition is restricted to a closed area of the device, isolated from the rest of the design by a fence of unused logic resources. Mitigation technique #2: WatchDog timer for Microblaze processor As it has been mentioned in the previous chapter, a watchdog timer peripheral has been included in the DRM in order to restart the processor if it crashes. Additionally, three protection mechanisms are proposed to detect and correct errors: Detection and Correction technique #1: memory scrubbing or configuration management The focus of this technique is the prevention of SEU accumulation in the FPGA configuration memory. Since our goal is to design and develop a self-managed FPGA and having into account that the Virtex- 5QV FPGA has an extremely low upset rate in configuration bits of 5 events per year (see reference [5]), an internal memory scrubber scheme will be implemented. Configuration memory scrubbing consists in re-writing the FPGA configuration memory while the design is actively running. This is different from a full device reconfiguration, which implies deleting the configuration memory before reloading the full bit stream. Configuration memory scrubbing is based on active partial reconfiguration of the desired configuration frames. Since the internal configuration management solution makes use of the internal ICAP port, and since the design does include an embedded processor core accessing the ICAP port to control the reconfiguratio...