Common use of Final Considerations Clause in Contracts

Final Considerations. The work presented in this paper proposes two area- optimized FPGA structures for the computation of the Xxxxxxxxxx modular multiplication algorithm for generic primes, targeting low–power IGLOO® 2 FPGAs from Mi- crosemi. The proposed structures impose a very low usage of the available FPGA resources while still achieving good performances. To achieve this performance with a low area, the Math Blocks and embedded memories were used to- gether with a careful scheduling to assure a full pipeline usage and a low number of computation cycles. While the first structure achieves the lowest area, the second one allows to approximately half the computation time at the cost of twice the amount of embedded memories and Math Blocks and only 35% more LUTs and registers. Future work will consist of adding wrapping and control logic to allow for the full computation of the ECC scalar multiplication. The main challenge will be to minimize the additional memory and control resources needed to store and process the intermediate values. References [1] X. X. Xxxxxxxxxx, “Modular Multiplication without Trial Division,” Mathematics of Computation, vol. 44, no. 170, pp. 519–521, 1985. [2] X. X. Xxxxxx, X. Xxxxxx, and X. Xxxxxxx, “A method for obtaining digital signatures and public-key cryptosystems,” Communications of the ACM, vol. 21, no. 2, pp. 120–126, feb 1978. [3] X. Xxxxxx, “Use of Elliptic Curves in Cryptography,” in Advances in Cryptology - CRYPTO 85 Proceedings, ser. Lecture Notes in Computer Science. Berlin, Germany: Springer Berlin / Heidelberg, 1986, vol. 218, pp. 417–426. [4] X. Xxxxxx, “Xxxxxxxxxx exponentiation needs no final subtractions,” Electronics Letters, vol. 35, no. 21, pp. 1831–1832, Oct 1999. [5] X. Xxxxxx, X. Xxxxx-Xxxxxxxx, and S. B. Örs, “Flexible Hardware Design for RSA and Elliptic Curve Cryptosystems,” in Topics in Cryptology – CT-RSA 2004, ser. Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2004, vol. 2964, pp. 250–263. [6] X. XxXxxx, X. XxXxxxx, and X. X. XxXxxxx, “FPGA Xxxxxxxxxx multiplier architectures - a comparison,” in Field-Programmable Cus- xxx Computing Machines, 2004. FCCM 2004. 12th Annual IEEE Symposium on, April 2004, pp. 279–282. [7] X. Xxxxxxx, X. Xxxxxxx, X. Xxxxx, X. Xxxxxxx, X. Xxxxxx, X. Xxxxxxx, and X. Xxxxxxxxxxx, “A compact FPGA-based architecture for elliptic curve cryptography over prime fields,” in Application-specific Systems Architectures and Processors (ASAP), 2010 21st IEEE International Conference on, July 2010, pp. 313–316. [8] X. Xxxxxxxx and X. Xxxxxxxxx, “Fast and Flexible Hardware Support for ECC Over Multiple Standard Prime Fields,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 22, no. 12, pp. 2661–2674, Dec 2014. [9] X. Xxxxx, X. Xxxx, X. X. Xxxxxxxxx, and I. S. Xxxxx, “Parallel crypto-devices for GF(p) elliptic curve multiplication resistant against side channel attacks,” Computers & Electrical Engineering, vol. 35, no. 2, pp. 329 – 338, 2009, circuits and Systems for Real-Time Security and Copyright Protection of Multimedia. [10] Microsemi, “IGLOO2 Product Information Brochure,” Microsemi, Tech. Rep., 2014. [Online]. Avail- able: xxxx://xxx.xxxxxxxxx.xxx/document-portal/doc_download/ 132013-igloo2-product-information-brochure [11] X. X. Xxx, X. Xxxx, and X. X. Xxxxxxx Xx., “Analyzing and comparing Xxxxxxxxxx multiplication algorithms,” Micro, IEEE, vol. 16, no. 3, pp. 26–33, Jun 1996. [12] X. Xxxxxxx and X. Xxxx, “A Scalable GF(p) Elliptic Curve Processor Architecture for Programmable Hardware,” in Cryptographic Hard- ware and Embedded Systems — CHES 2001, ser. Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2001, vol. 2162, pp. 348–363. [13] X. Xxxxxx and X. Xxxx, “Efficient Xxxxxxxxxx Multiplier for Pairing and Elliptic Curve Based Cryptography,” in Communication Systems, Networks Digital Signal Processing (CSNDSP), 2014 9th Interna- tional Symposium on, July 2014, pp. 255–260. [14] S. B. Örs, X. Xxxxxx, X. Xxxxxxx, and X. Xxxxxxxxxx, “Hardware implementation of a Xxxxxxxxxx modular multiplier in a systolic array,” in Parallel and Distributed Processing Symposium, 2003. Proceedings. International, April 2003, p. 8. [15] X. X. Xxxxxxxx and A. D. Xxxxx, “Novel algorithms and hardware architectures for xxxxxxxxxx multiplication over gf(p),” Cryptology ePrint Archive, Report 2015/696, 2015. [16] X. Xxxxxx, X. Xx-Xxxxxx, X. Xxxxxxxxx, X. X. Xxxxxx, X. Xxxxxxxxxx, X. Xxxxxxxx, and X. Xxxxxxxx, “A systolic hardware architectures of xxxxxxxxxx modular multiplication for public key cryptosystems,” Cryptology ePrint Archive, Report 2016/487, 2016. [17] X. Xxxxx, X. Xxxxxxx, and X. Xxxxxxx, “Flexible fpga-based architec- tures for curve point multiplication over gf(p),” in 2016 Euromicro Conference on Digital System Design (DSD), Aug 2016, pp. 107–114. [18] X. Xxxx, X. Xxxxxxx, X. Xxxxxx, and X. Xxxxxxxx, “An FPGA imple- mentation of a GF(p) ALU for encryption processors,” Microproces- sors and Microsystems, vol. 28, no. 5–6, pp. 253 – 260, 2004, special Issue on FPGAs: Applications and Designs.

Appears in 7 contracts

Samples: repository.ubn.ru.nl, Mem 64x17, repository.ubn.ru.nl

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