Hardware Implementations comparison. In this section the comparison of the performance of the single and double core architectures is presented. On Table 10 the execution time of the different architectures is compared. As shown in the Table due to the initialization time the 2 core architecture is slower for small number of bins. The initialization of 2 more streams leads to this increase in execution time. While the number of bins increases, the increase in performance approaches 1.5x, as the initialization overhead becomes a small fraction of the total execution time. The increase in performance is less than 2, even if the processing in hardware is doubled, because preprocessing in software is needed in order to split the pdfs in half. Num of Bins HW1(sec) HW2(sec) SpeedUp 100 0.031 0.036 0.86 500 0.036 0.037 0.97 1000 0.046 0.047 0.98 2000 0.1 0.077 1.3 5000 0.45 0.31 1.45 10000 1.8 1.1 1.6 20000 7.1 4.9 1.45 40000 30.5 19.7 1.55 Table 10:MI 1core Vs 2core HW implementations The throughput presented on Table 11 is not the real PCI throughput but the application throughput, as in the time factor the initialization of the DFE is taken into account. For small number of bins the throughput of the 2 core implementation is lower than the 1 core, as the initialization time remains the main factor of the execution time. With the increase of the number of bins the throughput reaches up to 900MB/s for the 2 core architecture approaching the theoretical PCI bandwidth for 5 streams, which is 1250MB/s. Also the 1 core architecture approaches the theoretical bandwidth, which is 750MB/s for 3 streams, by achieving up to 670MB/s. As mentioned above the throughput calculated is the application throughput and not only the hardware call throughput. Num of Bins HW1(MB/sec) HW2(MB/sec) 100 3.8 2.8 500 83 68 1000 261 213 2000 480 519 5000 667 806 10000 667 909 20000 676 816 40000 629 812 Table 11:Throughput comparison 3 streams –vs. 6 streams In 3.3.1.3 three implementations are presented, that achieve better performance increase than our implementation. It is not safe to compare this implementation with the ones presented in [18], [19], and [20] as the speedups mentioned consider different applications and Image related datasets. Image values could be represented with 8 bits allowing the better utilization of the available bandwidth, which would allow our implementation to achieve even greater performance.
