Addressing D3. 2 objectives 7
Addressing D3. 2 objectives This section focuses on the presentation of the objectives for the deliverable D3.2, as they were described in the QualiMaster Description of Work (DoW). Table 1shows our actions on the D3.1 objectives and where in this deliverable more details can be found. Task s Objective Specific actions undertaken according to D3.2 objectives Sections where more details can be found Task 3.1 Identify and analyse algorithms that will be accelerated through hardware Two new algorithms, Mutual Information and Transfer Entropy, were designed, taking into account the I/O issues and the algorithm profiling. Section 3.3.1 – Mutual Information Section 3.4.1 – Transfer Entropy Task 3.2 Develop an initial translation of the proposed stream processing algorithms on reconfigurable technology, offering special-purpose hardware-based accelerators We present the initial reconfigurable-based architectures for the ECM- sketches, the Xxxxxxx- Xxxxxxx, the Mutual Information, the Transfer Entropy and the SVM algorithms. Section 3.1.2 – ECM Sketches Architecture Section 3.2.2 –Xxxxxxx-Xxxxxxx Algorithm Architecture Section 3.3.2 – Mutual Information Algorithm Architecture Section 3.4.2 –Transfer Entropy Algorithm Architecture Section 3.5.3 –SVM Algorithm Architecture Provide technical restrictions and the related tradeoffs of reconfigurable hardware with respect to the initial translation of the proposed algorithmic tasks Some initial technical restrictions and tradeoffs are presented. First, we describe the restrictions for all the implemented algorithms and how the algorithm hardware- software partitioning takes place, e.g. for most of the algorithms we build the necessary data structures on software, while the main processing workload takes place in reconfigurable logic. Second, we describe the restrictions on the reconfigurable resources, e.g., internal memory, arithmetic operators, I/O busses that restrict the parallelization level of the proposed implementations. Last, we describe in details the mappings of the internal Section 3.1.2 – ECM Sketches Architecture Section 3.2.2 –Xxxxxxx-Xxxxxxx Algorithm Architecture Section 3.3.2 – Mutual Information Algorithm Architecture Section 3.4.2 –Transfer Entropy Algorithm Architecture Section 3.5.3 –SVM Algorithm Architecture resources so that we achieve fine grained and/or coarse grained parallelization.
