Inconsistent operations Sample Clauses

Inconsistent operations. To identify cross-platform and cross-evaluator inconsistent oper- ations, we have systematically reviewed the implementations of op- erations on the software/hardware platforms listed in Table 2 (cov- ering different software, different processor micro-architectures, and various numbers of logical cores in the same processor), and investigated all the operations defined in ONNX [7] operator set version 7 – a total number of 100. We identify the inconsistent operations by analyzing their two essential sources: 1. Non-associativity of floating-point operations 2. Standard-incompliant floating-point optimizations Non-associativity. Floating-point operations, as defined in the IEEE-754 standard [1], are not associative [33, 59, 81]. Thus, any computation that consists of multiple floating-point operations must specify the order of the operations, which is expressed as a computation graph, a.k.a. a circuit. Otherwise, with different circuit representations, a computation that is consistent in real numbers becomes inconsistent in floating-point numbers. Unfortunately, an operation only has a mathematical definition, which implies an ambiguous circuit representation. We observe that an operation may be interpreted into different circuit representa- tions on different software/hardware platforms, for performance reasons. For example, Figure 8 illustrates three possible circuits for a ReduceSum operation that aggregates eight float64 numbers: Circuit (a) shows the straightforward for-loop implementation; (b) shows the implementation using 128-bit SIMD instructions (e.g. Xxxxx Xxxxx, Xxxxxxx Xxx, Xxxx Xxxxx, Xxxx Xxxx, et al. SSE); (c) shows the implementation using 256-bit SIMD instruc- tions (e.g. AVX). Besides the SIMD width, we notice that the circuit may also depend on the number of threads, the cache size, and the summation algorithm. Sum + (a) Sum +
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