Results and Related Work. In order to properly evaluate the proposed structures, experimental results were compared with the state-of-the- art in Table 1. However, only previous works with multipli- cation timing results are depicted. Other works considering low latency and/or high throughput are not discussed, such as [12], [13]. Since they require significantly more FPGA resources, thus not resulting in a meaningful comparison. Considering an efficiency metric of the inverse of area (LUT + Register) times latency (µs), the second structure is able to achieve an efficiency of 784 being 40% more 0 27 + 17 44 + 44 17 44 44 0 MEM1 64x17 44 27 17 0 >> 17 >> 17
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Samples: repository.ubn.ru.nl, repository.ubn.ru.nl, repository.ubn.ru.nl
Results and Related Work. In order to properly evaluate the proposed structures, experimental results were compared with the state-of-the- art in Table 1. However, only previous works with multipli- cation timing results are depicted. Other works considering low latency and/or high throughput are not discussed, such as [12], [13]. Since they require significantly more FPGA resources, thus not resulting in a meaningful comparison. Considering an efficiency metric of the inverse of area (LUT + Register) times latency (µs), the second structure is able to achieve an efficiency of 784 being 40% more 0 27 + 17 44 + 44 17 44 44 0 MEM1 64x17 44 27 17 0 >> 17 >> 1717 27 0
Appears in 1 contract
Samples: Mem 64x17