Target Architecture Sample Clauses
Target Architecture. The baseline switch architecture is the same as reported in the previous Section 2 and reported in Fig.1. It relies on a stall/go flow control protocol and implements distributed routing by means of a route selection logic located at each input port. Failure of a switch input or output port and their associated switch internal sub-blocks can be viewed as the failure of the connected link. The diagnosis strategy proposed in this section will therefore target this requirement and will provide an indication of whether input and output ports of a switch are operational or not. As the cooperative testing strategy of Section 2, each switch can in turn test its several internal instances of the same sub-blocks (crossbar muxes, communication channels, port arbiters, routing modules) concurrently by means of pseudo-random patterns. The testing framework of Section 2, which comes up with one of the lowest testing latencies reported in the open literature for similar single stuck-at fault coverages, will be used for the sake of comparison as a lower bound for testing latency.
Target Architecture. The Cyclone for STMicro currently supports STM8A/S/L, STM32, and SPC56 targets. The user may select the target architecture from the drop-down list.
Target Architecture. Without lack of generality, we use the xpipesLite switch architecture [3] to prove viability of our testing methodology in a realistic NoC setting. The baseline switch architecture is illustrated in Fig.1. It implements both input and output buffering and relies on wormhole switching. The crossing latency is 1 cycle in the link and 1 cycle in the switch itself. Flit width assumed in this document is 32 bits, but can be easily varied. Without lack of generality, in this report the size of the output buffers is 6 flits, while it is 2 flits for the input buffers. This switch relies on a stall/go flow control protocol. It requires two control wires: one going forward and flagging data availability (”valid”) and one going backward and signaling either a condition of buffer filled (”stall”) or of buffer free (”go”). The switch architecture is extremely modular and exposes a large structural redundancy, i.e., a port-arbiter, a crossbar multiplexer and an output buffer are instantiated for each output port, while a routing module is cascaded to the buffer stage of each input port. This common feature to all switch architectures will be intensively exploited in this work. We implement distributed routing by means of a route selection logic located at each input port. Forwarding tables are usually adopted for this purpose, although they feature poor area and delay scalability with network size [24]. The possibility to implement logic-based distributed routing (LBDR) while retaining the flexibility of forwarding tables has been recently demonstrated in [25]. In practice, LBDR consists of a selection logic of the target switch output port relying on a few switch-specific configuration bits (namely routing Rxy, connectivity Cz and deroute bits drt). The number of these bits (14 in this case) is orders of magnitude less than the size of a forwarding table, yet makes the routing mechanism reconfigurable.
(a) illustrating the conditions that select the output port north UNj for routing. The pre-processed direction of packet destination Nj/Sj/Wj/Ej is an input together with the routing and the connectivity bits. In some cases (see [25] for details), deroutes are needed to properly route packets, and the associated logic is reported in Fig.2(b). LBDR supports the most widely used algorithms for irregular topologies and can be used on a 2D mesh as well as on roughly 60% of the irregular topologies derived from a 2D mesh, like ARBITER NORTH INPUT WEST LBDR WEST OUTPUT NORTH A...
Target Architecture. The Cyclone for Renesas supports R8C, RH850 (Cyclone Rev. C Only), RL78 (Cyclone Rev. C Only), RX (Cyclone Rev. C Only), H8 or H8S/Tiny, M16C, M16C/80, and M32C targets. The user may select the target architecture from the drop-down list.
5.1.1.1 R8C Devices Figure 5-3 shows the R8C specification configuration. Figure 5-3: R8C Class Settings