Bulk CMOS definition
Examples of Bulk CMOS in a sentence
Bhuva, et al., "Single-Event Charge Collection and Upset in 40-nm Dual- and Triple- Well Bulk CMOS SRAMs" IEEE Trans.
Demonstrate a complete AC Coupled first level packaging solution in both Bulk CMOS and SOI.
Such disclosure of Specific Results and/or Background Know-How shall not occur prior to L1 of the applicable Bulk CMOS, and must be subject to a written agreement between IFX and such recipient Third Party that, at a minimum, shall have a term of confidentiality consistent with that set forth the Agreement, and that limits such recipient’s use of such information in accordance with terms and conditions consistent to those set forth in the Agreement.
Lawrence, J.F. Ross, N.F. Haddad, R.A. Reed, D.R. Albrecht, “Soft Error Sensitivities in 90nm Bulk CMOS SRAMs”, Radiation Effects Data Workshop, NSREC 2009, pp.
The Parties agree to commence joint development activities for 300mm Wafer 45nm Bulk CMOS semiconductor manufacturing process technologies based on "SF" Bulk CMOS technology roadmap for the base process, the high performance process, and the low power process that are generally competitive in complexity, schedule, and performance as set forth as "Strategic Technology Objectives" in Exhibit A2 (hereinafter referred to as "Strategic Goals"), with the goal of agreeing on such Strategic Goals by *****.
IFX shall have the right (in addition to its other rights under this Section 7 of this Exhibit XX) to disclose the Specific Results and Background Know-How from a Bulk Project, as part of a license of substantially the entirety of IFX’s applicable Bulk CMOS as set forth in 7.11.1(A), 7.11.1 (B), and 7.11.2.
The foregoing license shall include the right for AMD to utilize one or more aspects of Bulk CMOS Information for the development and qualification of their own, proprietary Bulk CMOS process (“Derivative Process”) and for developing, engineering, manufacturing, using, marketing, selling, servicing and otherwise disposing of Integrated Circuits other than SOI Integrated Circuits utilizing such Derivative Process, such Integrated Circuits being designed by any party.
Chuang, C.H. Diaz, and M.S. Liang, TSMC10:45 a.m.11.5 High Performance Sub-40 nm Bulk CMOS with Dopant Confinement Layer (DCL) Technique as a Strain Booster, H.Ohta, N.Tamura, H.Fukutome, M.Tajima*, K.
In either case, prior to making such determinations IBM shall consult with AMD, who shall provide its input as to the applicability of such elements to a Bulk CMOS process; provided, however, that IBM shall have the right to make any and all final decisions as to designation and application of such elements to its Bulk CMOS process.
For the avoidance of doubt, in addition to Specific Results designated as Bulk CMOS Information or Industry Standard Information as described in this section 3.4, Bulk CMOS Information and Industry Standard Information shall include those items listed in Exhibit K attached hereto.