Intel Xeon Phi Architecture Sample Clauses

Intel Xeon Phi Architecture. Compact It uses all four threads of a core before it begins using the threads of subsequent cores. Balanced It maps threads on different cores until all the cores have at least one thread, as done in the scatter policy. However, when multiple threads need to use the same core, the balanced policy ensures that threads with consecutive IDs are close to each other, in con- trast to what is done by the scatter policy. Scatter It allocates the threads as evenly as possible over the whole pro- cessor such that consecutive threads are executed in different cores. Table 3.1: Thread affinity policies code in the inner loop is c[j] = a[j]∗b[j]+c[j]. The outer loop is distributed among the available threads using OpenMP. For example, having 48 threads and ITR = 48 ∗ 106 each of them executes 106 ∗ 16 operations. The inner loop is unrolled to optimize the program execution speed. The second micro-benchmark code is performing 48 ∗ 106 three reads, and one write memory access pattern (constitutes the inner loop) for ITR times (constitutes the outer loop). Listing A.2 shows the micro-benchmark program for measuring band- width. The key line of the code in the inner loop is c[j] = a[j] ∗ b[j] + c[j]. The inner loop is distributed among the available threads using OpenMP. We measure the computation cost of arithmetic operations on different data for- mats (i.e., double-precision floating-point and integer) and provide the performances of the micro-benchmark code.