Synthesizable RTL definition

Synthesizable RTL means the deliverables identified in Schedule 1 Part C Section 1.

Synthesizable RTL means (i) the rtl vectors identified in Schedule 1, Section 2, Part C item C1 and C2 of this Agreement for the ARM946E-S Core; and (ii) the rtl identified in Schedule 1, Section 3, Part C item C1 of this Agreement for the ARM966E-S Core.

Synthesizable RTL means the Verilog HDL files identified in the relevant Parthus Platform Definition Statement. 1.21. “Trademarks” means the trademarks identified in Exhibit D 1.22. “Updates” means any enhancements and modifications including but not limited to Error corrections to any Product including any associated Documentation and any embodied Intellectual Property, developed by or for Silaria from time to time, and which Silaria releases generally to the public, but does not include new revisions of a Product generally defined as one that includes new functionality. 1.23. “Use” means the conversion of the Synthesizable RTL for the relevant product or device to a synthesized gate level netlist (SGN), or other subsequent implementation of such SGN. Life-cycle maintenance of a product or device including each or all of the fixing of bugs in, increasing the performance of and increasing the yield of the product or device shall not be considered a use. Use of a Parthus Platform by a customer solely to repair Errors subsequent to a payment for a Use by that customer for that specific Parthus Platform will not be considered as an additional Use requiring an additional fee. 1.24. “Use Fee Cap” means a limit to the number of Use fees associated with the instantiation of the Products into each End User Licensed Products required of the End User and due to Silaria for each Parthus Platform. Use Fee Caps for the Silaria Products are outlined in Exhibit C.

Examples of Synthesizable RTL in a sentence

• In respect of each implementation of an ARM Core, LICENSEE shall use the relevant Synthesizable RTL to generate a pre-layout synthesized netlist, (each a "PRE-LAYOUT SYNTHESIZED NETLIST").

• So far, these attempts have been successful only on a small scale (i.e. simple networks) [15], which shows the High Abstraction Specification Specification Design Space Back−of−the−envelope calculations Abstract executable models Cycle−accurate models Function High Effort Synthesizable RTL models Influence of deleted component Design Space Processor 1 Processor 2 Processor 3 bus Memory Figure 1.

• So far, these attempts have been successful only on a small scale (i.e. simple networks) [15], which shows theHigh AbstractionSpecificationSpecification DesignSpaceBack−of−the−envelope calculations Abstract executable models Cycle−accurate models Function High Effort Synthesizable RTL modelsInfluence of deleted component DesignSpace Processor 1 Processor 2 Processor 3 bus Memory Figure 1.

• Bid Templates Annexure 1 -specifications-Part 1 Item Specifications Sl. NoSpecificationsCompliance (Yes /No)Offered SpecificationsRe1.1Automatic conversion ofC-based code to RTL 1.2Inputs Support:SystemC,C, C++ 1.3Outputs support: Synthesizable RTL in Verilog/VHDL format 1.4Ability to specify the targettechnology and synthesis libraries.

• Bid Templates General Specification for High Level Synthesis EDA Tool -part 1 Item Specifications Sl. NoSpecificationsCompliance (Yes /No)Offered SpecificationsRe1.1Automatic conversion of C-based code to RTL 1.2Inputs Support:SystemC,C,C++ 1.3Outputs support: Synthesizable RTL in Verilog/VHDL format 1.4Ability to specify the targettechnology and synthesis libraries.

• BirbasSYNTHESIS (SDS)Formal Generation of Synthesizable RTL from Regular Programs 40M.

More Definitions of Synthesizable RTL

Synthesizable RTL means the deliverables identified in Section 1 Part C Section 1 of this Annex 1.

Synthesizable RTL means the Verilog HDL files identified in the relevant Parthus Platform Definition Statement.