Fault Models. In synchronous message-based distributed systems, a fault is typically defined as a message that was not transmitted when it was expected or a message that was transmitted but not received or received but not accepted, i.e., deemed invalid by a receiver. Thus, the fault is either associated with the source node of the message, the corresponding link between the source node and the destination node, or the destination node. Consequently, there are two viewpoints, node-centric and link-centric, and thus, there are two ways of modeling faults. In the node-centric model, which we refer to as the node-fault model, the faults are associated with the source node of the message and all fault manifestations between the source and the destination nodes for the messages from that source count as a single fault, which is specially the case when the faults are associated with a Byzantine faulty node [5, 6, 16, 17]. In this model all links are assumed to be good. Miner et al. [16] for instance, model the absence of a link as a link fault and even though both nodes and links failures are considered, they abstractly model link failures as failures of the source node. In the link-centric model, which we refer to as the link-fault model, a fault is associated with the communication means connecting the source node to the destination node. In this model, all nodes are assumed to be good and an invalid message at the receiving node is counted as a single fault for the corresponding input link. Thus, from the global perspective, a Byzantine faulty node manifests as one or more link failures. A link-fault model introduced by Xxxxxx et al. [18] is called perception-based hybrid fault model, where faults are viewed from the perspective of the receiving nodes. Faults are associated with their input links, and all nodes are assumed to be good. They argued that since F faulty nodes can produce at most F faulty perceptions in any node, the link-fault model is compatible with the traditional node-fault model and so, all existing lower bound and impossibility results remain valid. r r
Fault Models. In order to properly test digital circuits we first have to define what kind of defects (faults) can appear in a digital system. Here is a short overview of those faults. Stuck-at fault model Stuck-at is widely used fault model and it is covering many different physical faults [AB94]. The concept of this fault is very simple, and for each line in the system two possible stuck-at faults may appear: stuck-at 0, and stuck-at 1. For this type of fault it is considered that the faulty line is in permanent faulty state giving a constant 0 or constant 1. Additionally, one can consider stuck-at faults lines at both inputs and output of logical gates or only at outputs. Considering only output stuck-at faults simplifies the test but doesn’t cover all that can be detected with a test for both input and output stuck-at faults. Delay fault model A delay defect is a defect that causes an extra delay in the circuit. An example is a spot defect that causes a resistive short or open. To make the delay testing problem solvable, delay defect behaviour must be abstracted to a delay fault. [WST08] Transition fault model The transition fault model is similar to the stuck-at fault model in many respects. The effect of a transition fault at any point P in a circuit is that any transition at P will not reach a scan flip-flop or a primary output within the stipulated clock period of the circuit. According to the transition fault model [6], there are two types of faults possible on all lines in the circuit: a slow-to-rise fault (STR) and a slow-to- fall fault (STF). A slow-to-rise fault at a node means that any transition from 0 to 1 on the node does not produce the correct result when the device is operating at its maximum operating frequency. Similarly, a slow-to-fall fault means that a transition from 1 to 0 on a node does not produce the correct result at full operating frequency. [JA03] The primary advantage of the TF model is that test generation does not need to consider circuit timing. A stuck-at fault test generator can be modified to meet the additional requirements for generating TF tests [WAI87]. Because a stuck-at fault can be considered a very slow TF, a TF test set will detect all the corresponding stuck-at faults. The TF model has more constraints than the stuck-at fault model, so the TF coverage is normally lower than stuck-at fault coverage. Top-off vectors can be generated to test the stuck-at faults not detected by the TF test set. The primary disadvantage of th...
