For Intel definition

For Intel. For Impinj: Xxxxxxxx Xxxxxxxxxxx [TBD] Intel Corporation Impinj, Inc. MS RA1 – 331 000 Xxxxx 00xx Xxxxxx 0000 XX 000xx Xxxxxx Xxxxx 000 Xxxxxxxxx, XX 00000 Xxxxxxx, XX 00000 000-000-0000 000-000-0000

For Intel. For Impinj:

For Intel. For Impinj: Xxxxxxxx Xxxxxxxxxxx Xxx Xxxxxxx Intel Corporation Impinj, Inc. MS RA1 - 331 000 Xxxxx 00xx Xxxxxx 0000 XX 00xx Xxxxxx Xxxxx 000 Xxxxxxxxx, XX 00000 Xxxxxxx, XX 00000 *** Indicates text has been omitted from this Exhibit pursuant to a confidential treatment request and has been filed separately with the Securities and Exchange Commission.

Examples of For Intel in a sentence

• For Intel, this would be the Director of Corporate Purchasing and/or the Vice President of Materials.

• For Aquantia: /s/ [*] For Intel: [*] By: /s/ Phil Delansay By /s/ Xxx Xxxxxxxxx Printed Name: Phil Delansay Printed name: Xxx Xxxxxxxxx Title: CEO Title: Sr. VP & GM, Digital Enterprise Group Date: January 15, 2009 Date: January 15, 2009 [*] = CERTAIN CONFIDENTIAL INFORMATION CONTAINED IN THIS DOCUMENT, MARKED BY BRACKETS, IS FILED WITH THE SECURITIES AND EXCHANGE COMMISSION PURSUANT TO RULE 406 OF THE SECURITIES ACT OF 1933, AS AMENDED.

• For Intel, we ran the attacks on a Skylake i5-6200U CPU with MPX support, and for AMD we evaluated both an E2-2000 and a Ryzen Threadripper 1920X.

• For Intel CPUs, the update routine is triggered by writing the virtual address where the microcode patch has been loaded to the MSR IA32_BIOS_UPDT_TRIG.

• For Intel, this would be the Director of Global Indirect Procurement and/or the Vice President of Materials.

• For Intel massive parallel meant up to 128 processors which was the limit due to the maximum dimension of the connection network.

• For Intel SSD, the gap between se- quential and random writes is small; still the value of α is less than 10 due to I/O batching.Clearly, the worst case insertion cost into a CLAM us- ing BufferHash for flash is α times more expensive than that of a traditional hash table without buffering—a tradi- tional hash table requires writing a random sector, while BufferHash sequentially writes the entire buffer.

• For Intel, we use sev- eral machines featuring an Intel Core i5-3470 CPU that has a 6 MiB last-level cache and 20 GiB memory.

• For Intel SGX, the protected memory (i.e., the enclave) is mapped to a special physical memory area called Enclave Page Cache (EPC), which is encrypted and cannot be directly accessed by other software, firmware, BIOS, and direct memory access (DMA).Attestation.

• For Intel SGX, EPC is a limited resource; the largest EPC size currently available on an existing Intel CPU is 93.5 MB, out of 128 MB Processor’s Reserved Memory (PRM).

More Definitions of For Intel

For Intel. For Impinj: Xxxxxxxx Xxxxxxxxxxx Xxx Xxxxxxx Intel Corporation Impinj, Inc. MS RA1 - 331 000 Xxxxx 00xx Xxxxxx 0000 XX 00xx Xxxxxx Xxxxx 000 Xxxxxxxxx, XX 00000 Xxxxxxx, XX 00000 Xxxxxxxx.Xxxxxxxxxxx@xxxxx.xxx @Xxxxxx.xxx (000) 000-0000 000-000-0000 *** Indicates that confidential treatment has been sought for this information

For Intel. Xxxxx Xxxxxx For NCD: Xxxxx XxXxxxx Program Manager Director, Product Planning Intel Corporation Network Computing Devices 0000 XX Xxxx Xxxxx Pkwy 000 X. Xxxxxxxx Ave. HF3-50 Mountain View, CA 94043 Xxxxxxxxx, XX 00000 phone: (000)000-0000 phone: (000)000-0000 fax: (000)000-0000 fax: (000)000-0000 email: email: xxxxxxx@xxx.xxxxx.xxx