Alarm 1 Pin. Programmable Alarm 1 Pin (PRG_ALRM1) is an output pin to the Host, operating with programmable logic. This pin can be re-programmed over MDIO registers to another MDIO alarm register while the module is in any steady state except Reset. CFP-MSA specifies the default function to be Receiver Loss of Signal (RX_LOS) indicator with active-high logic.
Alarm 1 Pin. Programmable Alarm Pin 1 (PRG_ALRM1) is an output pin to the Host, operating with programmable logic. It can be re-programmed over MDIO registers to another MDIO alarm register while the module is in any steady state except Reset. MSA specifies the default function to be High Power On (HIPWR_ON) indicator with active-high logic. The 40G and 100G applications for which the CFP is designed have numerous PMDs or port types which require specialized optoelectronic components which dissipate significant electrical power. The CFP MSA is designating that there be an intermediate state between the Low-Power state to the Module-Ready state, the TX-Off state. This state and default alarm function provides a defined state and signal where the CFP
Alarm 1 Pin. Programmable Alarm Pin 1 (PRG_ALRM1) is an output pin to the Host, operating with programmable logic. It can be re-programmed over MDIO registers at run-time to another MDIO alarm register. The CFP MSA specifies the default function to be RXS (Receiver Synch and Frequency Lock) indicator with active-high logic. As a hardware pin function this alarm is intended to be a hardware response which flags when the digital receiver circuitry (PLL, DLL or other) is outside the expected frequency range. Note that some applications will utilize a microcontroller based alarm which will result in slower response times. When this function is mapped to a non-MSA Default alarm the timing will correspond to typical MDIO response times. Receiver Circuit CDR / PLL / DLL RXS Unlocked Locked MSA Default PRG_ALRM1 t_RXS_on t_RXS_off Figure 2-3: RXS (Receiver Signal) Timing Diagram
