BSP PERFORMANCE AND TESTING Sample Clauses

BSP PERFORMANCE AND TESTING. 7.2.1 Flat compilation flow There are two compilation flows for OpenCL designs. The first is the regular flow where the IP components such as memories, PCIe and IO connections are locked down in a fixed location. This guarantees that the OpenCL designs will work regardless of how low the compiled kernel clock frequency is. This ensures the critical components such as the PCIe and DDR memories always meet timing. For a flat flow, no components are locked down and therefore there is no guarantee that the critical components always meet timing. A flat flow has advantages in that extra functionality can be added to the BSP without a major rework to the BSP floor planning. Given that the OPERA BSP is to be continuously improved over the course of the project a flat flow will be used for initial OpenCL design and MICMAC port. Compilation of existing software using a flat flow have proven that critical components of the design still meet timing with a flat flow, if the PCIe is de-rated to Gen2. De-rating of the PCIe to Gen2 has no significant impact (see 7.2.4). Figure 17: Example flat build showing the base IP (PCIe, etc) in red (Arria 10 660-SOC) With the flat flow, there is no base region and the Altera tools can place the kernel logic amongst the board logic. So, whilst not all logic can be used, there are no floor planned regions where the kernel logic cannot be placed. This leads to a lower board resource usage than for a fixed floor planned BSP. The resource of the flat BSP is given below. FPGA resource type: FPGA Prototype Board Total Resource (10AS066H3F34E2SG) opera_ax066 Built with 16.1.1 ALMS FFs DSPs RAMs 251680 1006720 1687 2131 23483 (9.33%) 93932 (9.33%) 231 (10.84%) Table 10 : FPGA prototype BSP resource use
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