Compilation and Verification Tools Sample Clauses

Compilation and Verification Tools. The aforementioned observations place a critical requirement on the TULIPP tool-chain – the need for including a state-of-the-art HLS tool. To satisfy this requirement, our tool-chain is based on Xilinx SDSoC (see Section 5.3), and Figure 17a shows an overview of the key interfaces within the tool-chain of the TULIPP Reference Platform (TRP). Xilinx SDSoC is a complete development environment for compute platforms that tightly integrate CPUs with an FPGA-fabric. Thus, it provides direct access to both a state-of-the-art compiler for the CPU code and the Vivado HLS tool. This enables the the developer to simply select functions for acceleration on the FPGA-fabric. Then, the tool-chain will generate the required CPU binaries and FPGA bitfile required for running the application on the platform. The default SDSoC tool-chain contains all necessary compilation and validation tools. Its C/C++ compiler and Xilinx Vivado HLS take a C/C++ implementation as input and emits executables. SDSoC requires that the developer uses command line arguments to select procedures for offloading to the FPGA with HLS. In addition, the developer can use pragma directives to control how each procedure is converted to RTL. Both the command line in- terface and pragma directives are Xilinx HLS specific. Standardising these interfaces would enable choosing different HLS tools within a single developer-facing tool.
Sample 1
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Related to Compilation and Verification Tools

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