Hardware vs. Software Sample Clauses

Hardware vs. Software. The results of the comparison of the hardware and software implementations are presented on the following Tables. In Table 8 the comparison of the software execution time with the hardware execution time with 1 MI calculation core is presented, while Table 9 presents the same comparison but with 2 cores running on the hardware. The experiments presented here and in the next section were done using 100.000 length time series for two random variables. The random variables represent stocks, while the time series are their values over time. The datasets were taken from the data provided by Spring. The software used in these experiments is the equivalent single thread implementation of the algorithm. It is written in C and the pdf estimation part is also used on the hardware implementation in the host code segment. As a first conclusion by the results it is clear that for small amounts of Bins the software implementation is much faster than the hardware. This happens because the hardware function call and the initialization of the streams need 5 - 30ms. On the other hand as the number of bins increases, the hardware performance increases, as the initialization time is a small fraction of the calculation time. The first architecture (1 MI calculation core) achieves a performance increase of up to 5.8x. For this implementation 3 of the 8 streams to the DFEs were used and only 5% of the available FPGA resources. Num of Bins SW(sec) HW1(sec) SpeedUp 100 0.002 0.031 0.06 500 0.025 0.036 0.69 1000 0.095 0.046 2 2000 0.4 0.1 4 5000 2.5 0.45 5.6 10000 10.3 1.8 5.7 20000 41.5 7.1 5.8 40000 159 30.5 5.3 Table 8:SW vs. HW MI calculation time with 1 core As mentioned above, there are 8 streams available for data streaming between the CPU and the DFE. In order to utilize more of the available bandwidth the pdfs were divided by two, which allows the use of 6 streams. Actually 5 streams are utilized as the pdf that was streamed R times is now streamed R/2 times instead. Also by using 2 processing cores the processing power of the hardware is doubled. This improvement allowed an increase on performance of up to 9.4x for large number of Bins. Equation (1) allows the parallelization of the algorithm. The maximum available bandwidth is the limiting factor as the 2 core implementation utilizes only 10% of the available FPGA resources while using 5 of the 8 available streams. Num of Bins SW(sec) HW2(sec) SpeedUp 100 0.002 0.036 0.05 500 0.025 0.037 0.68 1000 0.095 0.047 2 2000 0.4 ...