Workloads and application Sample Clauses

Workloads and application mapping For the evaluations we use a collection of applications from the SPLASH-2 benchmark [17] with the default parameters defined in [16]. We have evaluated several configurations of multiple application instances mapped to the same CMP for different numbers of memory controllers, in order to detect indications of congestion problems as we scale the number of memory controllers from 1 to 4 (giving 2 to 8 memory controller channels). The applications are statically mapped to the chip when the experiment is set up. Applications are mapped to completely fill the chip, giving a fair share of cores to each application. Every batch consists of a single application type from the benchmark suite rather than being composed of a collection of mixed applications. This regularity makes it significantly easier to generate relevant statistics and spot trends in the results, such as to get averaged results for the execution time comparison. Running a mix of applications will even out some of the variations of the communication demand over time, but the conclusions will still be the same. See Figure 4 for an example of the mapping of 12 concurrent applications with 2 memory controllers. Parameter Configuration Core x86 L1 cache 16 KBytes Instructions + 16 KBytes Data Total 32 KBytes per core 2 cycles latency 2-way associativity 64 bytes block size L2 cache 256 Kbytes per core 20 cycles latency 4-way associativity 64 bytes block size Main memory 1 Gbyte total 200 cycles latency Coherence protocol MOESI CMP, directory-based Table 1: CMP configuration. Parameter Configuration Topology 10 × 10 2-dimensional regular mesh Routing mechanism LBDR + SR Packet switching Virtual cut-through (VCTlite) [12] Buffer queue size 12 flits Flit-size 8 bytes Table 2: Network-on-chip configuration.
Sample 1
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