and 1.2 definition

and 1.2. The implementation of these scenarios follows the indications defined in the section before. For this purpose, we use the OCM and DDR memory of the ZYNQ device. The DDR memory is used for writing and reading the data of the CPUs. Instead, the OCM memory is used for storing the values of the CRCs which are calculated by the CPUs. In addition, as shown in Figure 30, the DDR memory of the ZYNQ device can be accessed by the CPUs through the snoop control unit and the shared memory or L2 cache, while the OCM memory can be accessed through the SCU without going through the L2 cache. The snoop control unit is analyzed in pattern PAT- CCMU –XX (see Section 4.2.2). Figure 30: ZYNQ 7000 – Interconnecting the OCM and DDR memory and the CPUs (Source [16]). This multi-core device is proprietary of Xilinx. Therefore, proprietary software tools such as Vivado and SDK are used for implementing these two scenarios (see Figure 31). Vivado software is used for defining the system architecture of the device, whereas the SDK software is used for implementing the application code. In this case, we use the SDK software for implementing the application code in C for the two CPUs of the ZYNQ device. The two CPUs implement the same functionality. The main difference is the CPU where the application is executed. Comparator Comparator Comparator Comparator CRC CPU0 CRC CPU1 CRC CPU0 CRC CPU1 Shared Memory Shared Memory OCM OCM Figure 31: Implementation of scenarios 1.1 and 1.2 for the ZYNQ-7000 device. Implementing scenario 1.3: This scenario is an extension of the scenarios 1.1 and 1.2 that implements the proposed CRC and comparator DD R DD R based solution in both the processing layer and the programmable logic of a multi-core device. In our case, the PS and the PL layers of the ZYNQ device are used for implementing this scenario. As defined before, the steps defined in the scenarios 1.1 and 1.2 are followed by this scenario to diagnose the shared memory. The major differences between these three scenarios lie in the execution environments of the applications and in the access methods to memories. Figure 32: ZYNQ 7000 – Interconnecting the OCM and the DDR memory, the CPUs and the PL (Source [16]). In the case of the ZYNQ device, as shown in Figure 32, the OCM memory can be accessed by the CPUs of the PS through the snoop control unit, while the DDR memory can be accessed through the snoop control unit and the L2 cache. On the other hand, the PL can access to the DRR directly throug...